laba3
This commit is contained in:
VJkook
commit
113709ff19
25
.gitignore
vendored
Normal file
25
.gitignore
vendored
Normal file
@ -0,0 +1,25 @@
|
||||
# Normal rules
|
||||
#.*
|
||||
*.a
|
||||
*.bin
|
||||
*.elf
|
||||
*.lst
|
||||
*.map
|
||||
*.swp
|
||||
|
||||
# Build tree
|
||||
/build-*
|
||||
|
||||
# VS Code
|
||||
.vscode/*
|
||||
!.vscode/settings.json
|
||||
!.vscode/tasks.json
|
||||
!.vscode/launch.json
|
||||
!.vscode/extensions.json
|
||||
!.vscode/*.code-snippets
|
||||
|
||||
# Local History for Visual Studio Code
|
||||
.history/
|
||||
|
||||
# Built Visual Studio Code Extensions
|
||||
*.vsix
|
||||
9
.vscode/extensions.json
vendored
Normal file
9
.vscode/extensions.json
vendored
Normal file
@ -0,0 +1,9 @@
|
||||
{
|
||||
"recommendations": [
|
||||
"dan-c-underwood.arm",
|
||||
"trond-snekvik.gnu-mapfiles",
|
||||
"keroc.hex-fmt",
|
||||
"zixuanwang.linkerscript",
|
||||
"marus25.cortex-debug"
|
||||
]
|
||||
}
|
||||
27
.vscode/launch.json
vendored
Normal file
27
.vscode/launch.json
vendored
Normal file
@ -0,0 +1,27 @@
|
||||
{
|
||||
// Используйте IntelliSense, чтобы узнать о возможных атрибутах.
|
||||
// Наведите указатель мыши, чтобы просмотреть описания существующих атрибутов.
|
||||
// Для получения дополнительной информации посетите: https://go.microsoft.com/fwlink/?linkid=830387
|
||||
"version": "0.2.0",
|
||||
"configurations": [
|
||||
{
|
||||
"name": "Debug (Qemu)",
|
||||
"cwd": "${workspaceFolder}",
|
||||
"executable": "main.elf",
|
||||
"request": "launch",
|
||||
"type": "cortex-debug",
|
||||
"runToEntryPoint": "_start",
|
||||
//"device": "STM32F103xx",
|
||||
"servertype": "qemu",
|
||||
"cpu": "cortex-m4",
|
||||
//"machine":"lm3s6965evb",
|
||||
"machine": "netduinoplus2",
|
||||
"showDevDebugOutput":"none",
|
||||
"svdFile": "svd/STM32F405.svd",
|
||||
"preLaunchTask": "build",
|
||||
//"serverpath": null,
|
||||
"serverArgs": ["-d", "in_asm,cpu_reset,page,strace,int"],
|
||||
// "serverArgs": ["-d", "in_asm,cpu_reset,page,strace,int", "-action", "panic=pause", "-no-shutdown"],
|
||||
}
|
||||
]
|
||||
}
|
||||
3
.vscode/settings.json
vendored
Normal file
3
.vscode/settings.json
vendored
Normal file
@ -0,0 +1,3 @@
|
||||
{
|
||||
"cortex-debug.variableUseNaturalFormat": false
|
||||
}
|
||||
73
.vscode/tasks.json
vendored
Normal file
73
.vscode/tasks.json
vendored
Normal file
@ -0,0 +1,73 @@
|
||||
{
|
||||
// See https://go.microsoft.com/fwlink/?LinkId=733558
|
||||
// for the documentation about the tasks.json format
|
||||
"version": "2.0.0",
|
||||
"tasks": [
|
||||
{
|
||||
"label": "build",
|
||||
"type": "process",
|
||||
"command": "make",
|
||||
//"args": ["--debug"],
|
||||
"icon": {"id":"file-binary"},
|
||||
"group": "build",
|
||||
"presentation": {
|
||||
// Reveal the output only if unrecognized errors occur.
|
||||
"reveal": "silent",
|
||||
"revealProblems": "onProblem"
|
||||
},
|
||||
"problemMatcher": [
|
||||
//"$gcc",
|
||||
{
|
||||
"owner": "gcc",
|
||||
"fileLocation": [
|
||||
"autoDetect",
|
||||
"${cwd}"
|
||||
],
|
||||
"pattern": {
|
||||
"regexp": "^(.*?):(\\d+):(\\d*):?\\s+(?:fatal\\s+)?(warning|error):\\s+(.*)$",
|
||||
"file": 1,
|
||||
"line": 2,
|
||||
"column": 3,
|
||||
"severity": 4,
|
||||
"message": 5
|
||||
}
|
||||
},
|
||||
{
|
||||
"owner": "ARMASM",
|
||||
"fileLocation":[
|
||||
"autoDetect",
|
||||
"${workspaceFolder}"
|
||||
],
|
||||
"pattern": {
|
||||
//"regexp": "^(.*?):(\\d+):(\\d*):?\\s+(?:fatal\\s+)?(warning|error):\\s+(.*)$",
|
||||
"regexp": "^(.*?):(\\d+):?\\s([Ee]rror|[Ww]arning)\\s*:\\s+(.+)$",
|
||||
"file": 1,
|
||||
"line": 2,
|
||||
//"location": 2,
|
||||
"severity": 3,
|
||||
"message": 4,
|
||||
}
|
||||
},
|
||||
// TODO: make errors
|
||||
//{
|
||||
// "owner": "make",
|
||||
// "pattern": {
|
||||
// "regexp": ""
|
||||
// }
|
||||
//}
|
||||
],
|
||||
},
|
||||
{
|
||||
"label": "clean",
|
||||
"type": "process",
|
||||
"command": "make",
|
||||
"args":["clean"],
|
||||
"icon": {"id":"trash"},
|
||||
"group":"none",
|
||||
"presentation": {
|
||||
// Reveal the output only if unrecognized errors occur.
|
||||
"reveal": "silent"
|
||||
},
|
||||
}
|
||||
]
|
||||
}
|
||||
201
ldscripts/gcc.ld
Normal file
201
ldscripts/gcc.ld
Normal file
@ -0,0 +1,201 @@
|
||||
/* Linker script to configure memory regions.
|
||||
* Need modifying for a specific board.
|
||||
* FLASH.ORIGIN: starting address of flash
|
||||
* FLASH.LENGTH: length of flash
|
||||
* RAM.ORIGIN: starting address of RAM bank 0
|
||||
* RAM.LENGTH: length of RAM bank 0
|
||||
*/
|
||||
/*
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K * /
|
||||
RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K * /
|
||||
}
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 /* 1024K */
|
||||
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x1C000 /* 112K */
|
||||
}
|
||||
|
||||
/* Linker script to place sections and symbol values. Should be used together
|
||||
* with other linker script that defines memory regions FLASH and RAM.
|
||||
* It references following symbols, which must be defined in code:
|
||||
* Reset_Handler : Entry of reset handler
|
||||
*
|
||||
* It defines following symbols, which code can use without definition:
|
||||
* __exidx_start
|
||||
* __exidx_end
|
||||
* __copy_table_start__
|
||||
* __copy_table_end__
|
||||
* __zero_table_start__
|
||||
* __zero_table_end__
|
||||
* __etext
|
||||
* __data_start__
|
||||
* __preinit_array_start
|
||||
* __preinit_array_end
|
||||
* __init_array_start
|
||||
* __init_array_end
|
||||
* __fini_array_start
|
||||
* __fini_array_end
|
||||
* __data_end__
|
||||
* __bss_start__
|
||||
* __bss_end__
|
||||
* __end__
|
||||
* end
|
||||
* __HeapLimit
|
||||
* __StackLimit
|
||||
* __StackTop
|
||||
* __stack
|
||||
*/
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text*)
|
||||
|
||||
KEEP(*(.init))
|
||||
KEEP(*(.fini))
|
||||
|
||||
/* .ctors */
|
||||
*crtbegin.o(.ctors)
|
||||
*crtbegin?.o(.ctors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||
*(SORT(.ctors.*))
|
||||
*(.ctors)
|
||||
|
||||
/* .dtors */
|
||||
*crtbegin.o(.dtors)
|
||||
*crtbegin?.o(.dtors)
|
||||
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||
*(SORT(.dtors.*))
|
||||
*(.dtors)
|
||||
|
||||
*(.rodata*)
|
||||
|
||||
KEEP(*(.eh_frame*))
|
||||
} > FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
/* To copy multiple ROM to RAM sections,
|
||||
* uncomment .copy.table section and,
|
||||
* define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.copy.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__copy_table_start__ = .;
|
||||
LONG (__etext)
|
||||
LONG (__data_start__)
|
||||
LONG (__data_end__ - __data_start__)
|
||||
LONG (__etext2)
|
||||
LONG (__data2_start__)
|
||||
LONG (__data2_end__ - __data2_start__)
|
||||
__copy_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* To clear multiple BSS sections,
|
||||
* uncomment .zero.table section and,
|
||||
* define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
|
||||
/*
|
||||
.zero.table :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__zero_table_start__ = .;
|
||||
LONG (__bss_start__)
|
||||
LONG (__bss_end__ - __bss_start__)
|
||||
LONG (__bss2_start__)
|
||||
LONG (__bss2_end__ - __bss2_start__)
|
||||
__zero_table_end__ = .;
|
||||
} > FLASH
|
||||
*/
|
||||
|
||||
/* Location counter can end up 2byte aligned with narrow Thumb code but
|
||||
__etext is assumed by startup code to be the LMA of a section in RAM
|
||||
which must be 4byte aligned */
|
||||
__etext = ALIGN (4);
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
|
||||
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
/* All data end */
|
||||
__data_end__ = .;
|
||||
|
||||
} > RAM
|
||||
|
||||
.bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > RAM
|
||||
|
||||
.heap (COPY):
|
||||
{
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
*(.heap*)
|
||||
__HeapLimit = .;
|
||||
} > RAM
|
||||
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (COPY):
|
||||
{
|
||||
*(.stack*)
|
||||
} > RAM
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
|
||||
}
|
||||
67
main.S
Normal file
67
main.S
Normal file
@ -0,0 +1,67 @@
|
||||
.syntax unified /* Использование синтаксиса ARM UAL */
|
||||
.arch armv7e-m /* Архитектура ARMv7-M */
|
||||
|
||||
/* Секция кода в ПЗУ */
|
||||
.text /* Указывает ассемблеру собирать эту секцию */
|
||||
.thumb /* Использование Thumb ISA */
|
||||
|
||||
.global _start /* Экспорт символа _start */
|
||||
/* Метка _start - начало программы */
|
||||
|
||||
.type _start, %function /* Указывает, что _start - функция */
|
||||
_start:
|
||||
b main /* Переход к функции main */
|
||||
|
||||
.thumb_func
|
||||
.global main
|
||||
.type main, %function
|
||||
main:
|
||||
ldr r0, =str1 /* Загружаем адрес строки в регистр r0 */
|
||||
ldr r1, =char_to_find /* Загружаем адрес искомого символа в регистр r1 */
|
||||
ldrb r1, [r1] /* Загружаем значение искомого символа в регистр r1 */
|
||||
bl strchr /* Вызываем функцию поиска символа (Выполняет переход на указанную метку и сохраняет адрес возврата в регистр lr) */
|
||||
|
||||
/* Остановка для проверки результата */
|
||||
stop:
|
||||
b stop /* Бесконечный цикл для остановки программы */
|
||||
|
||||
.thumb_func
|
||||
.global strchr
|
||||
.type strchr, %function
|
||||
|
||||
/* Реализация функции strchr */
|
||||
strchr:
|
||||
.L_search:
|
||||
ldrb r3, [r0] /* Загружаем следующий символ из строки в r3 и увеличиваем r0 на 1 (загружает байт из памяти в регистр) */
|
||||
cbz r3, .L_not_found /*(сравнение с 0) Если достигли конца строки (нулевой символ), переходим к .L_not_found */
|
||||
|
||||
cmp r3, r1 /* cmp Сравнивает текущий символ с искомым символом */
|
||||
beq .L_found /* Если совпадают, переходим к .L_found (флаг Z) */
|
||||
adds r0, #1
|
||||
b .L_search /* Иначе продолжаем поиск (безусловный переход)*/
|
||||
|
||||
.L_not_found:
|
||||
movs r0, #0 /* Если символ не найден, возвращаем 0 (перемещаем в r0 значенние 0) */
|
||||
@ bx lr /* Возврат из функции */
|
||||
|
||||
.L_found:
|
||||
@ subs r0, #1 /* Корректируем указатель, так как он был увеличен после загрузки (вычитает 1) */
|
||||
|
||||
bx lr /* Возврат из функции */
|
||||
|
||||
.size strchr, . - strchr /* Указывает размер функции strchr */
|
||||
|
||||
|
||||
|
||||
|
||||
/* Секция константных данных в ПЗУ */
|
||||
.data
|
||||
.type str1, %object
|
||||
str1:
|
||||
.asciz "Hell" /* Строка, в которой ищем символ */
|
||||
|
||||
.type char_to_find, %object
|
||||
char_to_find:
|
||||
.asciz "q" /* Искомый символ */
|
||||
|
||||
.end /* Конец файла */
|
||||
13
main.hex
Normal file
13
main.hex
Normal file
@ -0,0 +1,13 @@
|
||||
:1000000000C001206D000000910000009100000080
|
||||
:10001000910000009100000091000000000000002D
|
||||
:10002000000000000000000000000000910000003F
|
||||
:10003000910000000000000091000000910000000D
|
||||
:100040009100000000F000B806480749097800F068
|
||||
:1000500001F8FEE703781BB18B4202D00130F9E7CB
|
||||
:100060000020704700000020050000200549064AD6
|
||||
:10007000064B9A42BEBF51F8040B42F8040BF8E756
|
||||
:10008000FFF7E0FF940000000000002008000020BF
|
||||
:04009000FEE700BFC8
|
||||
:0800940048656C6C007100006E
|
||||
:040000030000006D8C
|
||||
:00000001FF
|
||||
73
makefile
Normal file
73
makefile
Normal file
@ -0,0 +1,73 @@
|
||||
include makefile.conf
|
||||
|
||||
NAME = main
|
||||
TARGET = $(NAME).elf
|
||||
|
||||
#VPATH=
|
||||
|
||||
OBJDIR = obj
|
||||
OUTDIR = bin
|
||||
|
||||
LDSCRIPTS = -L. -L$(BASE)/ldscripts -T gcc.ld
|
||||
|
||||
DEFINE = -D __NO_SYSTEM_INIT
|
||||
|
||||
#ASFLAGS=
|
||||
#CFLAGS = -std=c99 -Og -g -Wall -ffreestanding
|
||||
LDFLAGS=-nostdlib $(ARCH_FLAGS) $(USE_SEMIHOST) $(LDSCRIPTS) $(DEFINE) $(DI) $(MAP)
|
||||
|
||||
SOURCES = $(wildcard *.s *.S *.c)
|
||||
HEADERS = $(wildcard *.h)
|
||||
#SOURCES = main.s
|
||||
|
||||
OBJECTS = $(SOURCES)
|
||||
OBJECTS := $(SOURCES:%.s=%.o)
|
||||
OBJECTS := $(OBJECTS:%.S=%.o)
|
||||
OBJECTS := $(OBJECTS:%.c=%.o)
|
||||
|
||||
all: build
|
||||
|
||||
build: $(NAME).elf $(NAME).hex size
|
||||
|
||||
envmake:
|
||||
@echo VARIABLES:
|
||||
@echo SHELL: $(SHELL)
|
||||
@echo STARTUP: $(STARTUP)
|
||||
@echo CFLAGS: $(CFLAGS)
|
||||
@echo CXXFLAGS: $(CXXFLAGS)
|
||||
@echo LDFLAGS: $(LDFLAGS)
|
||||
@echo OBJECTS: $(OBJECTS)
|
||||
|
||||
$(TARGET): $(SOURCES) $(STARTUP)
|
||||
$(LINK.s) $^ $(LDLIBS) -o $@
|
||||
|
||||
#$(TARGET): $(OBJECTS) $(STARTUP)
|
||||
# $(LINK.o) $^ $(LDLIBS) -o $@
|
||||
|
||||
# This pattern rule extract binary from an ELF executable
|
||||
# filename.bin is built from filename.elf
|
||||
%.bin: %.elf
|
||||
$(OBJCOPY) $< -O binary $@
|
||||
|
||||
# Produce firmware file in Intel Hex format
|
||||
%.hex: %.elf
|
||||
$(OBJCOPY) $< -O ihex $@
|
||||
|
||||
# Disassemble
|
||||
%.lst: %.elf
|
||||
$(OBJDUMP) -d $< > $@
|
||||
|
||||
#.PHONY: build
|
||||
|
||||
size:
|
||||
# @echo Size: $(TARGET)
|
||||
@$(SIZE) $(TARGET)
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
$(RM) $(TARGET) *.o *.elf *.bin *.hex *.map *.lst
|
||||
|
||||
#.SUFFIXES:
|
||||
#.SUFFIXES: .s .S .c .o .elf .bin .hex .ln
|
||||
|
||||
#.DEFAULT_TARGET: all
|
||||
40
makefile.conf
Normal file
40
makefile.conf
Normal file
@ -0,0 +1,40 @@
|
||||
# Selecting Core
|
||||
CORTEX_M=4
|
||||
|
||||
# Use newlib-nano. To disable it, specify USE_NANO=
|
||||
USE_NANO=--specs=nano.specs
|
||||
|
||||
# Use seimhosting or not
|
||||
USE_SEMIHOST=--specs=rdimon.specs
|
||||
USE_NOHOST=--specs=nosys.specs
|
||||
|
||||
CORE=CM$(CORTEX_M)
|
||||
BASE=.
|
||||
|
||||
# Compiler & Linker
|
||||
AS=arm-none-eabi-as
|
||||
AR=arm-none-eabi-ar
|
||||
CC=arm-none-eabi-gcc
|
||||
CXX=arm-none-eabi-g++
|
||||
OBJCOPY=arm-none-eabi-objcopy
|
||||
OBJDUMP=arm-none-eabi-objdump
|
||||
SIZE=arm-none-eabi-size
|
||||
|
||||
# Options for specific architecture
|
||||
ARCH_FLAGS=-mthumb -mcpu=cortex-m$(CORTEX_M)
|
||||
|
||||
# Startup code
|
||||
STARTUP=$(BASE)/startup/startup_ARM$(CORE).S
|
||||
|
||||
# -Os -flto -ffunction-sections -fdata-sections to compile for code size
|
||||
CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections
|
||||
CXXFLAGS=$(CFLAGS)
|
||||
|
||||
# Generate debug information
|
||||
DI=-Wa,-g
|
||||
|
||||
# Link for code size
|
||||
GC=-Wl,--gc-sections
|
||||
|
||||
# Create map file
|
||||
MAP=-Wl,-Map=$(NAME).map
|
||||
263
startup/startup_ARMCM0.S
Normal file
263
startup/startup_ARMCM0.S
Normal file
@ -0,0 +1,263 @@
|
||||
/* File: startup_ARMCM0.S
|
||||
* Purpose: startup file for Cortex-M0 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.0
|
||||
* Date: 16 August 2013
|
||||
*
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
.syntax unified
|
||||
.arch armv6-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0xc00
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 1
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
blt .L_loop0_0_done
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
b .L_loop0_0
|
||||
|
||||
.L_loop0_0_done:
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
subs r3, r2
|
||||
ble .L_loop1_done
|
||||
|
||||
.L_loop1:
|
||||
subs r3, #4
|
||||
ldr r0, [r1,r3]
|
||||
str r0, [r2,r3]
|
||||
bgt .L_loop1
|
||||
|
||||
.L_loop1_done:
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
blt .L_loop2_0_done
|
||||
str r0, [r1, r2]
|
||||
b .L_loop2_0
|
||||
.L_loop2_0_done:
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
|
||||
subs r2, r1
|
||||
ble .L_loop3_done
|
||||
|
||||
.L_loop3:
|
||||
subs r2, #4
|
||||
str r0, [r1, r2]
|
||||
bgt .L_loop3
|
||||
.L_loop3_done:
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
.end
|
||||
257
startup/startup_ARMCM3.S
Normal file
257
startup/startup_ARMCM3.S
Normal file
@ -0,0 +1,257 @@
|
||||
/* File: startup_ARMCM3.S
|
||||
* Purpose: startup file for Cortex-M3 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.0
|
||||
* Date: 16 August 2013
|
||||
*
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0xc00
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
.end
|
||||
257
startup/startup_ARMCM4.S
Normal file
257
startup/startup_ARMCM4.S
Normal file
@ -0,0 +1,257 @@
|
||||
/* File: startup_ARMCM4.S
|
||||
* Purpose: startup file for Cortex-M4 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.0
|
||||
* Date: 16 August 2013
|
||||
*
|
||||
/* Copyright (c) 2011 - 2013 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0xc00
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
.end
|
||||
257
startup/startup_ARMCM7.S
Normal file
257
startup/startup_ARMCM7.S
Normal file
@ -0,0 +1,257 @@
|
||||
/* File: startup_ARMCM7.S
|
||||
* Purpose: startup file for Cortex-M7 devices. Should use with
|
||||
* GCC for ARM Embedded Processors
|
||||
* Version: V2.0
|
||||
* Date: 01 August 2014
|
||||
*
|
||||
/* Copyright (c) 2011 - 2014 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
.syntax unified
|
||||
.arch armv7e-m
|
||||
|
||||
.section .stack
|
||||
.align 3
|
||||
#ifdef __STACK_SIZE
|
||||
.equ Stack_Size, __STACK_SIZE
|
||||
#else
|
||||
.equ Stack_Size, 0xc00
|
||||
#endif
|
||||
.globl __StackTop
|
||||
.globl __StackLimit
|
||||
__StackLimit:
|
||||
.space Stack_Size
|
||||
.size __StackLimit, . - __StackLimit
|
||||
__StackTop:
|
||||
.size __StackTop, . - __StackTop
|
||||
|
||||
.section .heap
|
||||
.align 3
|
||||
#ifdef __HEAP_SIZE
|
||||
.equ Heap_Size, __HEAP_SIZE
|
||||
#else
|
||||
.equ Heap_Size, 0
|
||||
#endif
|
||||
.globl __HeapBase
|
||||
.globl __HeapLimit
|
||||
__HeapBase:
|
||||
.if Heap_Size
|
||||
.space Heap_Size
|
||||
.endif
|
||||
.size __HeapBase, . - __HeapBase
|
||||
__HeapLimit:
|
||||
.size __HeapLimit, . - __HeapLimit
|
||||
|
||||
.section .isr_vector
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler */
|
||||
.long HardFault_Handler /* Hard Fault Handler */
|
||||
.long MemManage_Handler /* MPU Fault Handler */
|
||||
.long BusFault_Handler /* Bus Fault Handler */
|
||||
.long UsageFault_Handler /* Usage Fault Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long 0 /* Reserved */
|
||||
.long SVC_Handler /* SVCall Handler */
|
||||
.long DebugMon_Handler /* Debug Monitor Handler */
|
||||
.long 0 /* Reserved */
|
||||
.long PendSV_Handler /* PendSV Handler */
|
||||
.long SysTick_Handler /* SysTick Handler */
|
||||
|
||||
/* External interrupts */
|
||||
.long Default_Handler
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
/* Firstly it copies data from read only memory to RAM. There are two schemes
|
||||
* to copy. One can copy more than one sections. Another can only copy
|
||||
* one section. The former scheme needs more instructions and read-only
|
||||
* data to implement than the latter.
|
||||
* Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
|
||||
|
||||
#ifdef __STARTUP_COPY_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of triplets, each of which specify:
|
||||
* offset 0: LMA of start of a section to copy from
|
||||
* offset 4: VMA of start of a section to copy to
|
||||
* offset 8: size of the section to copy. Must be multiply of 4
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r4, =__copy_table_start__
|
||||
ldr r5, =__copy_table_end__
|
||||
|
||||
.L_loop0:
|
||||
cmp r4, r5
|
||||
bge .L_loop0_done
|
||||
ldr r1, [r4]
|
||||
ldr r2, [r4, #4]
|
||||
ldr r3, [r4, #8]
|
||||
|
||||
.L_loop0_0:
|
||||
subs r3, #4
|
||||
ittt ge
|
||||
ldrge r0, [r1, r3]
|
||||
strge r0, [r2, r3]
|
||||
bge .L_loop0_0
|
||||
|
||||
adds r4, #12
|
||||
b .L_loop0
|
||||
|
||||
.L_loop0_done:
|
||||
#else
|
||||
/* Single section scheme.
|
||||
*
|
||||
* The ranges of copy from/to are specified by following symbols
|
||||
* __etext: LMA of start of the section to copy from. Usually end of text
|
||||
* __data_start__: VMA of start of the section to copy to
|
||||
* __data_end__: VMA of end of the section to copy to
|
||||
*
|
||||
* All addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
.L_loop1:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .L_loop1
|
||||
#endif /*__STARTUP_COPY_MULTIPLE */
|
||||
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* There are two schemes too. One can clear multiple BSS sections. Another
|
||||
* can only clear one section. The former is more size expensive than the
|
||||
* latter.
|
||||
*
|
||||
* Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
|
||||
* Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
|
||||
*/
|
||||
#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
|
||||
/* Multiple sections scheme.
|
||||
*
|
||||
* Between symbol address __copy_table_start__ and __copy_table_end__,
|
||||
* there are array of tuples specifying:
|
||||
* offset 0: Start of a BSS section
|
||||
* offset 4: Size of this BSS section. Must be multiply of 4
|
||||
*/
|
||||
ldr r3, =__zero_table_start__
|
||||
ldr r4, =__zero_table_end__
|
||||
|
||||
.L_loop2:
|
||||
cmp r3, r4
|
||||
bge .L_loop2_done
|
||||
ldr r1, [r3]
|
||||
ldr r2, [r3, #4]
|
||||
movs r0, 0
|
||||
|
||||
.L_loop2_0:
|
||||
subs r2, #4
|
||||
itt ge
|
||||
strge r0, [r1, r2]
|
||||
bge .L_loop2_0
|
||||
|
||||
adds r3, #8
|
||||
b .L_loop2
|
||||
.L_loop2_done:
|
||||
#elif defined (__STARTUP_CLEAR_BSS)
|
||||
/* Single BSS section scheme.
|
||||
*
|
||||
* The BSS section is specified by following symbols
|
||||
* __bss_start__: start of the BSS section.
|
||||
* __bss_end__: end of the BSS section.
|
||||
*
|
||||
* Both addresses must be aligned to 4 bytes boundary.
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.L_loop3:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .L_loop3
|
||||
#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
|
||||
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
bl SystemInit
|
||||
#endif
|
||||
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
bl __START
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Default_Handler
|
||||
.type Default_Handler, %function
|
||||
Default_Handler:
|
||||
b .
|
||||
.size Default_Handler, . - Default_Handler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, Default_Handler
|
||||
.endm
|
||||
|
||||
def_irq_handler NMI_Handler
|
||||
def_irq_handler HardFault_Handler
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SVC_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler PendSV_Handler
|
||||
def_irq_handler SysTick_Handler
|
||||
def_irq_handler DEF_IRQHandler
|
||||
|
||||
.end
|
||||
76
svd/ARMCM0.svd
Normal file
76
svd/ARMCM0.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM0</name> <!-- name of part-->
|
||||
<series>ARM Cortex M0</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M0 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM0</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>false</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>false</vtorPresent>
|
||||
<nvicPrioBits>2</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMCM0P.svd
Normal file
76
svd/ARMCM0P.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM0P</name> <!-- name of part-->
|
||||
<series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M0+ based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM0+</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>false</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>false</vtorPresent>
|
||||
<nvicPrioBits>2</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMCM1.svd
Normal file
76
svd/ARMCM1.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM1</name> <!-- name of part-->
|
||||
<series>ARM Cortex M0+</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M0+ based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM1</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>false</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>false</vtorPresent>
|
||||
<nvicPrioBits>2</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
103
svd/ARMCM23.svd
Normal file
103
svd/ARMCM23.svd
Normal file
@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM23</name> <!-- name of part-->
|
||||
<series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M23 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM23</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMCM3.svd
Normal file
76
svd/ARMCM3.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM3</name> <!-- name of part-->
|
||||
<series>ARM Cortex M3</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M3 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM3</name>
|
||||
<revision>r2p1</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
103
svd/ARMCM33.svd
Normal file
103
svd/ARMCM33.svd
Normal file
@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM33</name> <!-- name of part-->
|
||||
<series>ARMv8-M Mainline</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M33 based device<./description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM33</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
103
svd/ARMCM35P.svd
Normal file
103
svd/ARMCM35P.svd
Normal file
@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM35P</name> <!-- name of part-->
|
||||
<series>ARMv8-M Mainline</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M35P based device<./description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM35P</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMCM4.svd
Normal file
76
svd/ARMCM4.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM4</name> <!-- name of part-->
|
||||
<series>ARM Cortex M4</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M4 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM4</name>
|
||||
<revision>r0p1</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
107
svd/ARMCM55.svd
Normal file
107
svd/ARMCM55.svd
Normal file
@ -0,0 +1,107 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2020 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM55</name> <!-- name of part-->
|
||||
<series>ARMv8.1-M Mainline</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M55 based device</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM55</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>true</fpuPresent>
|
||||
<fpuDP>true</fpuDP>
|
||||
<dspPresent>true</dspPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<pmuPresent>true</pmuPresent>
|
||||
<pmuNumEventCnt>12</pmuNumEventCnt>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
80
svd/ARMCM7.svd
Normal file
80
svd/ARMCM7.svd
Normal file
@ -0,0 +1,80 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 -2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMCM7</name> <!-- name of part-->
|
||||
<series>ARM Cortex M7</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-M7 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>CM7</name>
|
||||
<revision>r1p1</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<icachePresent>true</icachePresent>
|
||||
<dcachePresent>true</dcachePresent>
|
||||
<itcmPresent>false</itcmPresent>
|
||||
<dtcmPresent>false</dtcmPresent>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMSC000.svd
Normal file
76
svd/ARMSC000.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMSC000</name> <!-- name of part-->
|
||||
<series>ARM Cortex SC000</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-SC000 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>SC000</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>false</vtorPresent>
|
||||
<nvicPrioBits>2</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
76
svd/ARMSC300.svd
Normal file
76
svd/ARMSC300.svd
Normal file
@ -0,0 +1,76 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMSC300</name> <!-- name of part-->
|
||||
<series>ARM Cortex SC300</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit Cortex-SC300 based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>SC300</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
103
svd/ARMv8MBL.svd
Normal file
103
svd/ARMv8MBL.svd
Normal file
@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMv8MBL</name> <!-- name of part-->
|
||||
<series>ARMv8-M Baseline</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit v8-M Baseline based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>ARMV8MBL</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
103
svd/ARMv8MML.svd
Normal file
103
svd/ARMv8MML.svd
Normal file
@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
|
||||
<!-- File naming: <vendor>_<part/series name>.svd -->
|
||||
|
||||
<!--
|
||||
Copyright (C) 2012 - 2018 Arm Limited. All rights reserved.
|
||||
|
||||
Purpose: System Viewer Description (SVD) Example (Schema Version 1.1)
|
||||
This is a description of a none-existent and incomplete device
|
||||
for demonstration purposes only.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
-->
|
||||
|
||||
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
|
||||
<vendor>ARM Ltd.</vendor> <!-- device vendor name -->
|
||||
<vendorID>ARM</vendorID> <!-- device vendor short name -->
|
||||
<name>ARMv8MML</name> <!-- name of part-->
|
||||
<series>ARMV8M</series> <!-- device series the device belongs to -->
|
||||
<version>1.0</version> <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
|
||||
<description>ARM 32-bit v8-M Baseline based device.</description>
|
||||
<licenseText> <!-- this license text will appear in header file. \n force line breaks -->
|
||||
ARM Limited (ARM) is supplying this software for use with Cortex-M\n
|
||||
processor based microcontroller, but can be equally used for other\n
|
||||
suitable processor architectures. This file can be freely distributed.\n
|
||||
Modifications to this file shall be clearly marked.\n
|
||||
\n
|
||||
THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
|
||||
OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
|
||||
ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
|
||||
CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
</licenseText>
|
||||
|
||||
<cpu> <!-- details about the cpu embedded in the device -->
|
||||
<name>ARMV8MML</name>
|
||||
<revision>r0p0</revision>
|
||||
<endian>little</endian>
|
||||
<mpuPresent>true</mpuPresent>
|
||||
<fpuPresent>false</fpuPresent>
|
||||
<vtorPresent>true</vtorPresent>
|
||||
<nvicPrioBits>3</nvicPrioBits>
|
||||
<vendorSystickConfig>false</vendorSystickConfig>
|
||||
<sauNumRegions>4</sauNumRegions>
|
||||
<sauRegionsConfig enabled="true" protectionWhenDisabled="s">
|
||||
<region enabled="true" name="SauRegion0">
|
||||
<base>0x00000000</base>
|
||||
<limit>0x001FFFE0</limit>
|
||||
<!-- secure / non-secure callable -->
|
||||
<access>c</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion1">
|
||||
<base>0x00200000</base>
|
||||
<limit>0x003FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion2">
|
||||
<base>0x20200000</base>
|
||||
<limit>0x203FFFE0</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
<region enabled="true" name="SauRegion3">
|
||||
<base>0x40000000</base>
|
||||
<limit>0x40040000</limit>
|
||||
<!-- non-secure -->
|
||||
<access>n</access>
|
||||
</region>
|
||||
</sauRegionsConfig>
|
||||
</cpu>
|
||||
|
||||
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
|
||||
<width>32</width> <!-- bus width is 32 bits -->
|
||||
<!-- default settings implicitly inherited by subsequent sections -->
|
||||
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
|
||||
and register that do not define "size" themselves -->
|
||||
<access>read-write</access> <!-- default access permission for all subsequent registers -->
|
||||
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
|
||||
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
|
||||
|
||||
</device>
|
||||
61681
svd/STM32F405.svd
Normal file
61681
svd/STM32F405.svd
Normal file
File diff suppressed because it is too large
Load Diff
11111
svd/lm3s6965.svd
Normal file
11111
svd/lm3s6965.svd
Normal file
File diff suppressed because it is too large
Load Diff
8492
svd/lm3s811.svd
Normal file
8492
svd/lm3s811.svd
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user