From 113709ff198439fa0892103ee389e059063f46a8 Mon Sep 17 00:00:00 2001 From: VJkook Date: Sat, 28 Dec 2024 15:19:43 +0300 Subject: [PATCH] laba3 --- .gitignore | 25 + .vscode/extensions.json | 9 + .vscode/launch.json | 27 + .vscode/settings.json | 3 + .vscode/tasks.json | 73 + ldscripts/gcc.ld | 201 + main.S | 67 + main.hex | 13 + makefile | 73 + makefile.conf | 40 + startup/startup_ARMCM0.S | 263 + startup/startup_ARMCM3.S | 257 + startup/startup_ARMCM4.S | 257 + startup/startup_ARMCM7.S | 257 + svd/ARMCM0.svd | 76 + svd/ARMCM0P.svd | 76 + svd/ARMCM1.svd | 76 + svd/ARMCM23.svd | 103 + svd/ARMCM3.svd | 76 + svd/ARMCM33.svd | 103 + svd/ARMCM35P.svd | 103 + svd/ARMCM4.svd | 76 + svd/ARMCM55.svd | 107 + svd/ARMCM7.svd | 80 + svd/ARMSC000.svd | 76 + svd/ARMSC300.svd | 76 + svd/ARMv8MBL.svd | 103 + svd/ARMv8MML.svd | 103 + svd/STM32F405.svd | 61681 +++++++++++++++++++++++++++++++++++++ svd/lm3s6965.svd | 11111 +++++++ svd/lm3s811.svd | 8492 +++++ 31 files changed, 84083 insertions(+) create mode 100644 .gitignore create mode 100644 .vscode/extensions.json create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 .vscode/tasks.json create mode 100644 ldscripts/gcc.ld create mode 100644 main.S create mode 100644 main.hex create mode 100644 makefile create mode 100644 makefile.conf create mode 100644 startup/startup_ARMCM0.S create mode 100644 startup/startup_ARMCM3.S create mode 100644 startup/startup_ARMCM4.S create mode 100644 startup/startup_ARMCM7.S create mode 100644 svd/ARMCM0.svd create mode 100644 svd/ARMCM0P.svd create mode 100644 svd/ARMCM1.svd create mode 100644 svd/ARMCM23.svd create mode 100644 svd/ARMCM3.svd create mode 100644 svd/ARMCM33.svd create mode 100644 svd/ARMCM35P.svd create mode 100644 svd/ARMCM4.svd create mode 100644 svd/ARMCM55.svd create mode 100644 svd/ARMCM7.svd create mode 100644 svd/ARMSC000.svd create mode 100644 svd/ARMSC300.svd create mode 100644 svd/ARMv8MBL.svd create mode 100644 svd/ARMv8MML.svd create mode 100644 svd/STM32F405.svd create mode 100644 svd/lm3s6965.svd create mode 100644 svd/lm3s811.svd diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..21b2199 --- /dev/null +++ b/.gitignore @@ -0,0 +1,25 @@ +# Normal rules +#.* +*.a +*.bin +*.elf +*.lst +*.map +*.swp + +# Build tree +/build-* + +# VS Code +.vscode/* +!.vscode/settings.json +!.vscode/tasks.json +!.vscode/launch.json +!.vscode/extensions.json +!.vscode/*.code-snippets + +# Local History for Visual Studio Code +.history/ + +# Built Visual Studio Code Extensions +*.vsix \ No newline at end of file diff --git a/.vscode/extensions.json b/.vscode/extensions.json new file mode 100644 index 0000000..0f4e80a --- /dev/null +++ b/.vscode/extensions.json @@ -0,0 +1,9 @@ +{ + "recommendations": [ + "dan-c-underwood.arm", + "trond-snekvik.gnu-mapfiles", + "keroc.hex-fmt", + "zixuanwang.linkerscript", + "marus25.cortex-debug" + ] +} \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..8178589 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,27 @@ +{ + // Используйте IntelliSense, чтобы узнать о возможных атрибутах. + // Наведите указатель мыши, чтобы просмотреть описания существующих атрибутов. + // Для получения дополнительной информации посетите: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Debug (Qemu)", + "cwd": "${workspaceFolder}", + "executable": "main.elf", + "request": "launch", + "type": "cortex-debug", + "runToEntryPoint": "_start", + //"device": "STM32F103xx", + "servertype": "qemu", + "cpu": "cortex-m4", + //"machine":"lm3s6965evb", + "machine": "netduinoplus2", + "showDevDebugOutput":"none", + "svdFile": "svd/STM32F405.svd", + "preLaunchTask": "build", + //"serverpath": null, + "serverArgs": ["-d", "in_asm,cpu_reset,page,strace,int"], + // "serverArgs": ["-d", "in_asm,cpu_reset,page,strace,int", "-action", "panic=pause", "-no-shutdown"], + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..af1664e --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cortex-debug.variableUseNaturalFormat": false +} \ No newline at end of file diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..620ba5e --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,73 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "process", + "command": "make", + //"args": ["--debug"], + "icon": {"id":"file-binary"}, + "group": "build", + "presentation": { + // Reveal the output only if unrecognized errors occur. + "reveal": "silent", + "revealProblems": "onProblem" + }, + "problemMatcher": [ + //"$gcc", + { + "owner": "gcc", + "fileLocation": [ + "autoDetect", + "${cwd}" + ], + "pattern": { + "regexp": "^(.*?):(\\d+):(\\d*):?\\s+(?:fatal\\s+)?(warning|error):\\s+(.*)$", + "file": 1, + "line": 2, + "column": 3, + "severity": 4, + "message": 5 + } + }, + { + "owner": "ARMASM", + "fileLocation":[ + "autoDetect", + "${workspaceFolder}" + ], + "pattern": { + //"regexp": "^(.*?):(\\d+):(\\d*):?\\s+(?:fatal\\s+)?(warning|error):\\s+(.*)$", + "regexp": "^(.*?):(\\d+):?\\s([Ee]rror|[Ww]arning)\\s*:\\s+(.+)$", + "file": 1, + "line": 2, + //"location": 2, + "severity": 3, + "message": 4, + } + }, + // TODO: make errors + //{ + // "owner": "make", + // "pattern": { + // "regexp": "" + // } + //} + ], + }, + { + "label": "clean", + "type": "process", + "command": "make", + "args":["clean"], + "icon": {"id":"trash"}, + "group":"none", + "presentation": { + // Reveal the output only if unrecognized errors occur. + "reveal": "silent" + }, + } + ] +} \ No newline at end of file diff --git a/ldscripts/gcc.ld b/ldscripts/gcc.ld new file mode 100644 index 0000000..6307d10 --- /dev/null +++ b/ldscripts/gcc.ld @@ -0,0 +1,201 @@ +/* Linker script to configure memory regions. + * Need modifying for a specific board. + * FLASH.ORIGIN: starting address of flash + * FLASH.LENGTH: length of flash + * RAM.ORIGIN: starting address of RAM bank 0 + * RAM.LENGTH: length of RAM bank 0 + */ +/* +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K * / + RAM (rwx) : ORIGIN = 0x10000000, LENGTH = 0x2000 /* 8K * / +} +*/ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x100000 /* 1024K */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x1C000 /* 112K */ +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.isr_vector)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + /* Location counter can end up 2byte aligned with narrow Thumb code but + __etext is assumed by startup code to be the LMA of a section in RAM + which must be 4byte aligned */ + __etext = ALIGN (4); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __end__ = .; + PROVIDE(end = .); + *(.heap*) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/main.S b/main.S new file mode 100644 index 0000000..d287e01 --- /dev/null +++ b/main.S @@ -0,0 +1,67 @@ +.syntax unified /* Использование синтаксиса ARM UAL */ +.arch armv7e-m /* Архитектура ARMv7-M */ + +/* Секция кода в ПЗУ */ +.text /* Указывает ассемблеру собирать эту секцию */ +.thumb /* Использование Thumb ISA */ + +.global _start /* Экспорт символа _start */ +/* Метка _start - начало программы */ + +.type _start, %function /* Указывает, что _start - функция */ +_start: + b main /* Переход к функции main */ + +.thumb_func +.global main +.type main, %function +main: + ldr r0, =str1 /* Загружаем адрес строки в регистр r0 */ + ldr r1, =char_to_find /* Загружаем адрес искомого символа в регистр r1 */ + ldrb r1, [r1] /* Загружаем значение искомого символа в регистр r1 */ + bl strchr /* Вызываем функцию поиска символа (Выполняет переход на указанную метку и сохраняет адрес возврата в регистр lr) */ + + /* Остановка для проверки результата */ +stop: + b stop /* Бесконечный цикл для остановки программы */ + +.thumb_func +.global strchr +.type strchr, %function + +/* Реализация функции strchr */ +strchr: +.L_search: + ldrb r3, [r0] /* Загружаем следующий символ из строки в r3 и увеличиваем r0 на 1 (загружает байт из памяти в регистр) */ + cbz r3, .L_not_found /*(сравнение с 0) Если достигли конца строки (нулевой символ), переходим к .L_not_found */ + + cmp r3, r1 /* cmp Сравнивает текущий символ с искомым символом */ + beq .L_found /* Если совпадают, переходим к .L_found (флаг Z) */ + adds r0, #1 + b .L_search /* Иначе продолжаем поиск (безусловный переход)*/ + +.L_not_found: + movs r0, #0 /* Если символ не найден, возвращаем 0 (перемещаем в r0 значенние 0) */ + @ bx lr /* Возврат из функции */ + +.L_found: + @ subs r0, #1 /* Корректируем указатель, так как он был увеличен после загрузки (вычитает 1) */ + + bx lr /* Возврат из функции */ + +.size strchr, . - strchr /* Указывает размер функции strchr */ + + + + +/* Секция константных данных в ПЗУ */ +.data +.type str1, %object +str1: + .asciz "Hell" /* Строка, в которой ищем символ */ + +.type char_to_find, %object +char_to_find: + .asciz "q" /* Искомый символ */ + +.end /* Конец файла */ diff --git a/main.hex b/main.hex new file mode 100644 index 0000000..2cc2c01 --- /dev/null +++ b/main.hex @@ -0,0 +1,13 @@ +:1000000000C001206D000000910000009100000080 +:10001000910000009100000091000000000000002D +:10002000000000000000000000000000910000003F +:10003000910000000000000091000000910000000D +:100040009100000000F000B806480749097800F068 +:1000500001F8FEE703781BB18B4202D00130F9E7CB +:100060000020704700000020050000200549064AD6 +:10007000064B9A42BEBF51F8040B42F8040BF8E756 +:10008000FFF7E0FF940000000000002008000020BF +:04009000FEE700BFC8 +:0800940048656C6C007100006E +:040000030000006D8C +:00000001FF diff --git a/makefile b/makefile new file mode 100644 index 0000000..2ebb07c --- /dev/null +++ b/makefile @@ -0,0 +1,73 @@ +include makefile.conf + +NAME = main +TARGET = $(NAME).elf + +#VPATH= + +OBJDIR = obj +OUTDIR = bin + +LDSCRIPTS = -L. -L$(BASE)/ldscripts -T gcc.ld + +DEFINE = -D __NO_SYSTEM_INIT + +#ASFLAGS= +#CFLAGS = -std=c99 -Og -g -Wall -ffreestanding +LDFLAGS=-nostdlib $(ARCH_FLAGS) $(USE_SEMIHOST) $(LDSCRIPTS) $(DEFINE) $(DI) $(MAP) + +SOURCES = $(wildcard *.s *.S *.c) +HEADERS = $(wildcard *.h) +#SOURCES = main.s + +OBJECTS = $(SOURCES) +OBJECTS := $(SOURCES:%.s=%.o) +OBJECTS := $(OBJECTS:%.S=%.o) +OBJECTS := $(OBJECTS:%.c=%.o) + +all: build + +build: $(NAME).elf $(NAME).hex size + +envmake: + @echo VARIABLES: + @echo SHELL: $(SHELL) + @echo STARTUP: $(STARTUP) + @echo CFLAGS: $(CFLAGS) + @echo CXXFLAGS: $(CXXFLAGS) + @echo LDFLAGS: $(LDFLAGS) + @echo OBJECTS: $(OBJECTS) + +$(TARGET): $(SOURCES) $(STARTUP) + $(LINK.s) $^ $(LDLIBS) -o $@ + +#$(TARGET): $(OBJECTS) $(STARTUP) +# $(LINK.o) $^ $(LDLIBS) -o $@ + +# This pattern rule extract binary from an ELF executable +# filename.bin is built from filename.elf +%.bin: %.elf + $(OBJCOPY) $< -O binary $@ + +# Produce firmware file in Intel Hex format +%.hex: %.elf + $(OBJCOPY) $< -O ihex $@ + +# Disassemble +%.lst: %.elf + $(OBJDUMP) -d $< > $@ + +#.PHONY: build + +size: +# @echo Size: $(TARGET) + @$(SIZE) $(TARGET) + +.PHONY: clean +clean: + $(RM) $(TARGET) *.o *.elf *.bin *.hex *.map *.lst + +#.SUFFIXES: +#.SUFFIXES: .s .S .c .o .elf .bin .hex .ln + +#.DEFAULT_TARGET: all diff --git a/makefile.conf b/makefile.conf new file mode 100644 index 0000000..cf34487 --- /dev/null +++ b/makefile.conf @@ -0,0 +1,40 @@ +# Selecting Core +CORTEX_M=4 + +# Use newlib-nano. To disable it, specify USE_NANO= +USE_NANO=--specs=nano.specs + +# Use seimhosting or not +USE_SEMIHOST=--specs=rdimon.specs +USE_NOHOST=--specs=nosys.specs + +CORE=CM$(CORTEX_M) +BASE=. + +# Compiler & Linker +AS=arm-none-eabi-as +AR=arm-none-eabi-ar +CC=arm-none-eabi-gcc +CXX=arm-none-eabi-g++ +OBJCOPY=arm-none-eabi-objcopy +OBJDUMP=arm-none-eabi-objdump +SIZE=arm-none-eabi-size + +# Options for specific architecture +ARCH_FLAGS=-mthumb -mcpu=cortex-m$(CORTEX_M) + +# Startup code +STARTUP=$(BASE)/startup/startup_ARM$(CORE).S + +# -Os -flto -ffunction-sections -fdata-sections to compile for code size +CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections +CXXFLAGS=$(CFLAGS) + +# Generate debug information +DI=-Wa,-g + +# Link for code size +GC=-Wl,--gc-sections + +# Create map file +MAP=-Wl,-Map=$(NAME).map diff --git a/startup/startup_ARMCM0.S b/startup/startup_ARMCM0.S new file mode 100644 index 0000000..bff4f02 --- /dev/null +++ b/startup/startup_ARMCM0.S @@ -0,0 +1,263 @@ +/* File: startup_ARMCM0.S + * Purpose: startup file for Cortex-M0 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 16 August 2013 + * +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv6-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long Default_Handler + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 1 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + blt .L_loop0_0_done + ldr r0, [r1, r3] + str r0, [r2, r3] + b .L_loop0_0 + +.L_loop0_0_done: + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .L_loop1_done + +.L_loop1: + subs r3, #4 + ldr r0, [r1,r3] + str r0, [r2,r3] + bgt .L_loop1 + +.L_loop1_done: +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + blt .L_loop2_0_done + str r0, [r1, r2] + b .L_loop2_0 +.L_loop2_0_done: + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 + + subs r2, r1 + ble .L_loop3_done + +.L_loop3: + subs r2, #4 + str r0, [r1, r2] + bgt .L_loop3 +.L_loop3_done: +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler SVC_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DEF_IRQHandler + + .end diff --git a/startup/startup_ARMCM3.S b/startup/startup_ARMCM3.S new file mode 100644 index 0000000..7d86998 --- /dev/null +++ b/startup/startup_ARMCM3.S @@ -0,0 +1,257 @@ +/* File: startup_ARMCM3.S + * Purpose: startup file for Cortex-M3 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 16 August 2013 + * +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long Default_Handler + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DEF_IRQHandler + + .end diff --git a/startup/startup_ARMCM4.S b/startup/startup_ARMCM4.S new file mode 100644 index 0000000..0724bf1 --- /dev/null +++ b/startup/startup_ARMCM4.S @@ -0,0 +1,257 @@ +/* File: startup_ARMCM4.S + * Purpose: startup file for Cortex-M4 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 16 August 2013 + * +/* Copyright (c) 2011 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv7e-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long Default_Handler + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DEF_IRQHandler + + .end diff --git a/startup/startup_ARMCM7.S b/startup/startup_ARMCM7.S new file mode 100644 index 0000000..0c199ad --- /dev/null +++ b/startup/startup_ARMCM7.S @@ -0,0 +1,257 @@ +/* File: startup_ARMCM7.S + * Purpose: startup file for Cortex-M7 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.0 + * Date: 01 August 2014 + * +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + .syntax unified + .arch armv7e-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0xc00 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .isr_vector + .align 2 + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts */ + .long Default_Handler + + .size __isr_vector, . - __isr_vector + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + +#ifndef __NO_SYSTEM_INIT + bl SystemInit +#endif + +#ifndef __START +#define __START _start +#endif + bl __START + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler DEF_IRQHandler + + .end diff --git a/svd/ARMCM0.svd b/svd/ARMCM0.svd new file mode 100644 index 0000000..14bf841 --- /dev/null +++ b/svd/ARMCM0.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM0 + ARM Cortex M0 + 1.0 + ARM 32-bit Cortex-M0 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM0 + r0p0 + little + false + false + false + 2 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM0P.svd b/svd/ARMCM0P.svd new file mode 100644 index 0000000..ff62fd4 --- /dev/null +++ b/svd/ARMCM0P.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM0P + ARM Cortex M0+ + 1.0 + ARM 32-bit Cortex-M0+ based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM0+ + r0p0 + little + false + false + false + 2 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM1.svd b/svd/ARMCM1.svd new file mode 100644 index 0000000..b51ac3b --- /dev/null +++ b/svd/ARMCM1.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM1 + ARM Cortex M0+ + 1.0 + ARM 32-bit Cortex-M0+ based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM1 + r0p0 + little + false + false + false + 2 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM23.svd b/svd/ARMCM23.svd new file mode 100644 index 0000000..3e01f8b --- /dev/null +++ b/svd/ARMCM23.svd @@ -0,0 +1,103 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM23 + ARMv8-M Baseline + 1.0 + ARM 32-bit Cortex-M23 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM23 + r0p0 + little + true + false + true + 3 + false + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM3.svd b/svd/ARMCM3.svd new file mode 100644 index 0000000..26e6acd --- /dev/null +++ b/svd/ARMCM3.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM3 + ARM Cortex M3 + 1.0 + ARM 32-bit Cortex-M3 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM3 + r2p1 + little + true + false + true + 3 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM33.svd b/svd/ARMCM33.svd new file mode 100644 index 0000000..ab66214 --- /dev/null +++ b/svd/ARMCM33.svd @@ -0,0 +1,103 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM33 + ARMv8-M Mainline + 1.0 + ARM 32-bit Cortex-M33 based device<./description> + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM33 + r0p0 + little + true + false + true + 3 + false + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM35P.svd b/svd/ARMCM35P.svd new file mode 100644 index 0000000..ac3f387 --- /dev/null +++ b/svd/ARMCM35P.svd @@ -0,0 +1,103 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM35P + ARMv8-M Mainline + 1.0 + ARM 32-bit Cortex-M35P based device<./description> + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM35P + r0p0 + little + true + false + true + 3 + false + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM4.svd b/svd/ARMCM4.svd new file mode 100644 index 0000000..a78bc8a --- /dev/null +++ b/svd/ARMCM4.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM4 + ARM Cortex M4 + 1.0 + ARM 32-bit Cortex-M4 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM4 + r0p1 + little + true + false + true + 3 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM55.svd b/svd/ARMCM55.svd new file mode 100644 index 0000000..b5be4ec --- /dev/null +++ b/svd/ARMCM55.svd @@ -0,0 +1,107 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM55 + ARMv8.1-M Mainline + 1.0 + ARM 32-bit Cortex-M55 based device + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM55 + r0p0 + little + true + true + true + true + true + 3 + false + true + 12 + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMCM7.svd b/svd/ARMCM7.svd new file mode 100644 index 0000000..7b69cb7 --- /dev/null +++ b/svd/ARMCM7.svd @@ -0,0 +1,80 @@ + + + + + + + + ARM Ltd. + ARM + ARMCM7 + ARM Cortex M7 + 1.0 + ARM 32-bit Cortex-M7 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + CM7 + r1p1 + little + true + false + true + 3 + false + true + true + false + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMSC000.svd b/svd/ARMSC000.svd new file mode 100644 index 0000000..261edd1 --- /dev/null +++ b/svd/ARMSC000.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMSC000 + ARM Cortex SC000 + 1.0 + ARM 32-bit Cortex-SC000 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + SC000 + r0p0 + little + true + false + false + 2 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMSC300.svd b/svd/ARMSC300.svd new file mode 100644 index 0000000..8beb8cc --- /dev/null +++ b/svd/ARMSC300.svd @@ -0,0 +1,76 @@ + + + + + + + + ARM Ltd. + ARM + ARMSC300 + ARM Cortex SC300 + 1.0 + ARM 32-bit Cortex-SC300 based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + SC300 + r0p0 + little + true + false + true + 3 + false + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMv8MBL.svd b/svd/ARMv8MBL.svd new file mode 100644 index 0000000..722ebe8 --- /dev/null +++ b/svd/ARMv8MBL.svd @@ -0,0 +1,103 @@ + + + + + + + + ARM Ltd. + ARM + ARMv8MBL + ARMv8-M Baseline + 1.0 + ARM 32-bit v8-M Baseline based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + ARMV8MBL + r0p0 + little + true + false + true + 3 + false + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/ARMv8MML.svd b/svd/ARMv8MML.svd new file mode 100644 index 0000000..bb2c998 --- /dev/null +++ b/svd/ARMv8MML.svd @@ -0,0 +1,103 @@ + + + + + + + + ARM Ltd. + ARM + ARMv8MML + ARMV8M + 1.0 + ARM 32-bit v8-M Baseline based device. + + ARM Limited (ARM) is supplying this software for use with Cortex-M\n + processor based microcontroller, but can be equally used for other\n + suitable processor architectures. This file can be freely distributed.\n + Modifications to this file shall be clearly marked.\n + \n + THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n + OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n + ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n + CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + + + + ARMV8MML + r0p0 + little + true + false + true + 3 + false + 4 + + + 0x00000000 + 0x001FFFE0 + + c + + + 0x00200000 + 0x003FFFE0 + + n + + + 0x20200000 + 0x203FFFE0 + + n + + + 0x40000000 + 0x40040000 + + n + + + + + 8 + 32 + + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + diff --git a/svd/STM32F405.svd b/svd/STM32F405.svd new file mode 100644 index 0000000..21351e6 --- /dev/null +++ b/svd/STM32F405.svd @@ -0,0 +1,61681 @@ + + + STM32F405 + 1.2 + STM32F405 + + + CM4 + r1p0 + little + false + false + 3 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + FPU + FPU interrupt + 81 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator + enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt + status + 6 + 1 + read-write + + + CEIS + Clock error interrupt + status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ENABLE + DCMI enable + 14 + 1 + + + EDM + Extended data mode + 10 + 2 + + + FCRC + Frame capture rate control + 8 + 2 + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + + + PCKPOL + Pixel clock polarity + 5 + 1 + + + ESS + Embedded synchronization + select + 4 + 1 + + + JPEG + JPEG format + 3 + 1 + + + CROP + Crop feature + 2 + 1 + + + CM + Capture mode + 1 + 1 + + + CAPTURE + Capture enable + 0 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + FSMC + Flexible static memory controller + FSMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FSMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + 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Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + 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read-only + 0x10006411 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + DBGMCU_CR + DBGMCU_CR + Control Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 16 + 1 + + + DBG_TIM8_STOP + DBG_TIM8_STOP + 17 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 18 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 19 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 20 + 1 + + + + + DBGMCU_APB1_FZ + DBGMCU_APB1_FZ + Debug MCU APB1 Freeze registe + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 0 + 1 + + + DBG_TIM3_STOP + DBG_TIM3 _STOP + 1 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 2 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 3 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 4 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 5 + 1 + + + DBG_TIM12_STOP + DBG_TIM12_STOP + 6 + 1 + + + DBG_TIM13_STOP + DBG_TIM13_STOP + 7 + 1 + + + DBG_TIM14_STOP + DBG_TIM14_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 11 + 1 + + + DBG_IWDEG_STOP + DBG_IWDEG_STOP + 12 + 1 + + + DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT + 22 + 1 + + + DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT + 23 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 25 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 26 + 1 + + + + + DBGMCU_APB2_FZ + DBGMCU_APB2_FZ + Debug MCU APB2 Freeze registe + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 0 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM9_STOP + TIM9 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM10_STOP + TIM10 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM11_STOP + TIM11 counter stopped when core is + halted + 18 + 1 + + + + + + + DMA2 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x400 + registers + + + DMA2_Stream0 + DMA2 Stream0 global interrupt + 56 + + + DMA2_Stream1 + DMA2 Stream1 global interrupt + 57 + + + DMA2_Stream2 + DMA2 Stream2 global interrupt + 58 + + + DMA2_Stream3 + DMA2 Stream3 global interrupt + 59 + + + DMA2_Stream4 + DMA2 Stream4 global interrupt + 60 + + + DMA2_Stream5 + DMA2 Stream5 global interrupt + 68 + + + DMA2_Stream6 + DMA2 Stream6 global interrupt + 69 + + + DMA2_Stream7 + DMA2 Stream7 global interrupt + 70 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + CHTIF6 + Stream x clear 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FS, SDIO and random number generator + clocks + 26 + 1 + + + PLLQ1 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 25 + 1 + + + PLLQ0 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 24 + 1 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) + entry clock source + 22 + 1 + + + PLLP1 + Main PLL (PLL) division factor for main + system clock + 17 + 1 + + + PLLP0 + Main PLL (PLL) division factor for main + system clock + 16 + 1 + + + PLLN8 + Main PLL (PLL) multiplication factor for + VCO + 14 + 1 + + + PLLN7 + Main PLL (PLL) multiplication factor for + VCO + 13 + 1 + + + PLLN6 + Main PLL (PLL) multiplication factor for + VCO + 12 + 1 + + + PLLN5 + Main PLL (PLL) multiplication factor for + VCO + 11 + 1 + + + PLLN4 + Main PLL (PLL) multiplication factor for + VCO + 10 + 1 + + + PLLN3 + Main PLL (PLL) multiplication factor for + VCO + 9 + 1 + + + PLLN2 + Main PLL (PLL) multiplication factor for + VCO + 8 + 1 + + + PLLN1 + Main PLL (PLL) multiplication factor for + VCO + 7 + 1 + + + PLLN0 + Main PLL (PLL) multiplication factor for + VCO + 6 + 1 + + + PLLM5 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 5 + 1 + + + PLLM4 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 4 + 1 + + + PLLM3 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 3 + 1 + + + PLLM2 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 2 + 1 + + + PLLM1 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 1 + 1 + + + PLLM0 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 0 + 1 + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output + 2 + 30 + 2 + read-write + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + + MCO1 + Microcontroller clock output + 1 + 21 + 2 + read-write + + + RTCPRE + HSE division factor for RTC + clock + 16 + 5 + read-write + + + PPRE2 + APB high-speed prescaler + (APB2) + 13 + 3 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 10 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS1 + System clock switch status + 3 + 1 + read-only + + + SWS0 + System clock switch status + 2 + 1 + read-only + + + SW1 + System clock switch + 1 + 1 + read-write + + + SW0 + System clock switch + 0 + 1 + read-write + + + + + CIR + CIR + clock interrupt register + 0xC + 0x20 + 0x00000000 + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + PLLI2SRDYC + PLLI2S ready interrupt + clear + 21 + 1 + write-only + + + PLLRDYC + Main PLL(PLL) ready interrupt + clear + 20 + 1 + write-only + + + HSERDYC + HSE ready interrupt clear + 19 + 1 + write-only + + + HSIRDYC + HSI ready interrupt clear + 18 + 1 + write-only + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + + PLLI2SRDYIE + PLLI2S ready interrupt + enable + 13 + 1 + read-write + + + PLLRDYIE + Main PLL (PLL) ready interrupt + enable + 12 + 1 + read-write + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + + CSSF + Clock security system interrupt + flag + 7 + 1 + read-only + + + PLLI2SRDYF + PLLI2S ready interrupt + flag + 5 + 1 + read-only + + + PLLRDYF + Main PLL (PLL) ready interrupt + flag + 4 + 1 + read-only + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + ETHMACRST + Ethernet MAC reset + 25 + 1 + + + DMA2RST + DMA2 reset + 22 + 1 + + + DMA1RST + DMA2 reset + 21 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + GPIOIRST + IO port I reset + 8 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + RNGRST + Random number generator module + reset + 6 + 1 + + + DCMIRST + Camera interface reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FSMCRST + Flexible static memory controller module + reset + 0 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACRST + DAC reset + 29 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2C2RST + I2C 2 reset + 22 + 1 + + + I2C1RST + I2C 1 reset + 21 + 1 + + + UART5RST + USART 5 reset + 20 + 1 + + + UART4RST + USART 4 reset + 19 + 1 + + + UART3RST + USART 3 reset + 18 + 1 + + + UART2RST + USART 2 reset + 17 + 1 + + + SPI3RST + SPI 3 reset + 15 + 1 + + + SPI2RST + SPI 2 reset + 14 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + TIM14RST + TIM14 reset + 8 + 1 + + + TIM13RST + TIM13 reset + 7 + 1 + + + TIM12RST + TIM12 reset + 6 + 1 + + + TIM7RST + TIM7 reset + 5 + 1 + + + TIM6RST + TIM6 reset + 4 + 1 + + + TIM5RST + TIM5 reset + 3 + 1 + + + TIM4RST + TIM4 reset + 2 + 1 + + + TIM3RST + TIM3 reset + 1 + 1 + + + TIM2RST + TIM2 reset + 0 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM11RST + TIM11 reset + 18 + 1 + + + TIM10RST + TIM10 reset + 17 + 1 + + + TIM9RST + TIM9 reset + 16 + 1 + + + SYSCFGRST + System configuration controller + reset + 14 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + SDIORST + SDIO reset + 11 + 1 + + + ADCRST + ADC interface reset (common to all + ADCs) + 8 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + TIM8RST + TIM8 reset + 1 + 1 + + + TIM1RST + TIM1 reset + 0 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock + enable + 30 + 1 + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + ETHMACPTPEN + Ethernet PTP clock enable + 28 + 1 + + + ETHMACRXEN + Ethernet Reception clock + enable + 27 + 1 + + + ETHMACTXEN + Ethernet Transmission clock + enable + 26 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 25 + 1 + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + BKPSRAMEN + Backup SRAM interface clock + enable + 18 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + GPIOIEN + IO port I clock enable + 8 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + RNGEN + Random number generator clock + enable + 6 + 1 + + + DCMIEN + Camera interface enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + FSMCEN + Flexible static memory controller module + clock enable + 0 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x40 + 0x20 + read-write + 0x00000000 + + + DACEN + DAC interface clock enable + 29 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + TIM2EN + TIM2 clock enable + 0 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + SYSCFGEN + System configuration controller clock + enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SDIOEN + SDIO clock enable + 11 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + TIM1EN + TIM1 clock enable + 0 + 1 + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power + mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during + Sleep mode + 30 + 1 + + + OTGHSLPEN + USB OTG HS clock enable during Sleep + mode + 29 + 1 + + + ETHMACPTPLPEN + Ethernet PTP clock enable during Sleep + mode + 28 + 1 + + + ETHMACRXLPEN + Ethernet reception clock enable during + Sleep mode + 27 + 1 + + + ETHMACTXLPEN + Ethernet transmission clock enable + during Sleep mode + 26 + 1 + + + ETHMACLPEN + Ethernet MAC clock enable during Sleep + mode + 25 + 1 + + + DMA2LPEN + DMA2 clock enable during Sleep + mode + 22 + 1 + + + DMA1LPEN + DMA1 clock enable during Sleep + mode + 21 + 1 + + + BKPSRAMLPEN + Backup SRAM interface clock enable + during Sleep mode + 18 + 1 + + + SRAM2LPEN + SRAM 2 interface clock enable during + Sleep mode + 17 + 1 + + + SRAM1LPEN + SRAM 1interface clock enable during + Sleep mode + 16 + 1 + + + FLITFLPEN + Flash interface clock enable during + Sleep mode + 15 + 1 + + + CRCLPEN + CRC clock enable during Sleep + mode + 12 + 1 + + + GPIOILPEN + IO port I clock enable during Sleep + mode + 8 + 1 + + + GPIOHLPEN + IO port H clock enable during Sleep + mode + 7 + 1 + + + GPIOGLPEN + IO port G clock enable during Sleep + mode + 6 + 1 + + + GPIOFLPEN + IO port F clock enable during Sleep + mode + 5 + 1 + + + GPIOELPEN + IO port E clock enable during Sleep + mode + 4 + 1 + + + GPIODLPEN + IO port D clock enable during Sleep + mode + 3 + 1 + + + GPIOCLPEN + IO port C clock enable during Sleep + mode + 2 + 1 + + + GPIOBLPEN + IO port B clock enable during Sleep + mode + 1 + 1 + + + GPIOALPEN + IO port A clock enable during sleep + mode + 0 + 1 + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power + mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep + mode + 7 + 1 + + + RNGLPEN + Random number generator clock enable + during Sleep mode + 6 + 1 + + + DCMILPEN + Camera interface enable during Sleep + mode + 0 + 1 + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power + mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FSMCLPEN + Flexible static memory controller module + clock enable during Sleep mode + 0 + 1 + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power + mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + DACLPEN + DAC interface clock enable during Sleep + mode + 29 + 1 + + + PWRLPEN + Power interface clock enable during + Sleep mode + 28 + 1 + + + CAN2LPEN + CAN 2 clock enable during Sleep + mode + 26 + 1 + + + CAN1LPEN + CAN 1 clock enable during Sleep + mode + 25 + 1 + + + I2C3LPEN + I2C3 clock enable during Sleep + mode + 23 + 1 + + + I2C2LPEN + I2C2 clock enable during Sleep + mode + 22 + 1 + + + I2C1LPEN + I2C1 clock enable during Sleep + mode + 21 + 1 + + + UART5LPEN + UART5 clock enable during Sleep + mode + 20 + 1 + + + UART4LPEN + UART4 clock enable during Sleep + mode + 19 + 1 + + + USART3LPEN + USART3 clock enable during Sleep + mode + 18 + 1 + + + USART2LPEN + USART2 clock enable during Sleep + mode + 17 + 1 + + + SPI3LPEN + SPI3 clock enable during Sleep + mode + 15 + 1 + + + SPI2LPEN + SPI2 clock enable during Sleep + mode + 14 + 1 + + + WWDGLPEN + Window watchdog clock enable during + Sleep mode + 11 + 1 + + + TIM14LPEN + TIM14 clock enable during Sleep + mode + 8 + 1 + + + TIM13LPEN + TIM13 clock enable during Sleep + mode + 7 + 1 + + + TIM12LPEN + TIM12 clock enable during Sleep + mode + 6 + 1 + + + TIM7LPEN + TIM7 clock enable during Sleep + mode + 5 + 1 + + + TIM6LPEN + TIM6 clock enable during Sleep + mode + 4 + 1 + + + TIM5LPEN + TIM5 clock enable during Sleep + mode + 3 + 1 + + + TIM4LPEN + TIM4 clock enable during Sleep + mode + 2 + 1 + + + TIM3LPEN + TIM3 clock enable during Sleep + mode + 1 + 1 + + + TIM2LPEN + TIM2 clock enable during Sleep + mode + 0 + 1 + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power + mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM11LPEN + TIM11 clock enable during Sleep + mode + 18 + 1 + + + TIM10LPEN + TIM10 clock enable during Sleep + mode + 17 + 1 + + + TIM9LPEN + TIM9 clock enable during sleep + mode + 16 + 1 + + + SYSCFGLPEN + System configuration controller clock + enable during Sleep mode + 14 + 1 + + + SPI1LPEN + SPI 1 clock enable during Sleep + mode + 12 + 1 + + + SDIOLPEN + SDIO clock enable during Sleep + mode + 11 + 1 + + + ADC3LPEN + ADC 3 clock enable during Sleep + mode + 10 + 1 + + + ADC2LPEN + ADC2 clock enable during Sleep + mode + 9 + 1 + + + ADC1LPEN + ADC1 clock enable during Sleep + mode + 8 + 1 + + + USART6LPEN + USART6 clock enable during Sleep + mode + 5 + 1 + + + USART1LPEN + USART1 clock enable during Sleep + mode + 4 + 1 + + + TIM8LPEN + TIM8 clock enable during Sleep + mode + 1 + 1 + + + TIM1LPEN + TIM1 clock enable during Sleep + mode + 0 + 1 + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL1 + RTC clock source selection + 9 + 1 + read-write + + + RTCSEL0 + RTC clock source selection + 8 + 1 + read-write + + + LSEBYP + External low-speed oscillator + bypass + 2 + 1 + read-write + + + LSERDY + External low-speed oscillator + ready + 1 + 1 + read-only + + + LSEON + External low-speed oscillator + enable + 0 + 1 + read-write + + + + + CSR + CSR + clock control & status + register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + WDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator + ready + 1 + 1 + read-only + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + SSCGR + SSCGR + spread spectrum clock generation + register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation + enable + 31 + 1 + + + SPREADSEL + Spread Select + 30 + 1 + + + INCSTEP + Incrementation step + 13 + 15 + + + MODPER + Modulation period + 0 + 13 + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SRx + PLLI2S division factor for I2S + clocks + 28 + 3 + + + PLLI2SNx + PLLI2S multiplication factor for + VCO + 6 + 9 + + + + + + + GPIOI + General-purpose I/Os + GPIO + 0x40022000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOH + 0x40021C00 + + + GPIOG + 0x40021800 + + + GPIOF + 0x40021400 + + + GPIOE + 0x40021000 + + + GPIOD + 0X40020C00 + + + GPIOC + 0x40020800 + + + GPIOJ + 0x40022400 + + + GPIOK + 0x40022800 + + + GPIOB + General-purpose I/Os + GPIO + 0x40020400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000280 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + 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1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x40020000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xA8000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y 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OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 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ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRM + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + MEM_MODE + 0 + 2 + + + + + PMC + PMC + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + Ethernet PHY interface + selection + 23 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control + register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell + power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + FRF + Frame format + 4 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + I2S2ext + 0x40003400 + + + I2S3ext + 0x40004000 + + + SPI4 + 0x40013400 + + SPI1 + SPI1 global interrupt + 35 + + + + SPI5 + 0x40015000 + + SPI1 + SPI1 global interrupt + 35 + + + + SPI6 + 0x40015400 + + SPI3 + SPI3 global interrupt + 51 + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + see Table 132. + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + see Table 132. + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + see Table 132. + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + see Table 132. + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x51 + registers + + + ADC + ADC1 global interrupt + 18 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + + RES + Resolution + 24 + 2 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 30 + 1 + + + EXTEN + External trigger enable for regular + channels + 28 + 2 + + + EXTSEL + External event select for regular + group + 24 + 4 + + + JSWSTART + Start conversion of injected + channels + 22 + 1 + + + JEXTEN + External trigger enable for injected + channels + 20 + 2 + + + JEXTSEL + External event select for injected + group + 16 + 4 + + + ALIGN + Data alignment + 11 + 1 + + + EOCS + End of conversion + selection + 10 + 1 + + + DDS + DMA disable selection (for single ADC + mode) + 9 + 1 + + + DMA + Direct memory access mode (for single + ADC mode) + 8 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D Converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + JDR1 + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR2 + JDR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR3 + JDR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR4 + JDR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + ADC + ADC2 global interrupts + 18 + + + + ADC3 + 0x40012200 + + ADC + ADC3 global interrupts + 18 + + + + USART6 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011400 + + 0x0 + 0x400 + registers + + + USART6 + USART6 global interrupt + 71 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + GTPR + GTPR + Guard time and prescaler + register + 0x18 + 0x20 + read-write + 0x0000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + + + USART1 + 0x40011000 + + USART1 + USART1 global interrupt + 37 + + + + USART2 + 0x40004400 + + USART2 + USART2 global interrupt + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 global interrupt + 39 + + + + DAC + Digital-to-analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt + enable + 29 + 1 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt + enable + 13 + 1 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + EN1 + DAC channel1 enable + 0 + 1 + + + + + SWTRIGR + SWTRIGR + software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + + + DHR12R1 + DHR12R1 + channel1 12-bit right-aligned data holding + register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + channel1 12-bit left aligned data holding + register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + channel1 8-bit right aligned data holding + register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + channel2 12-bit right aligned data holding + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + channel2 12-bit left aligned data holding + register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + channel2 8-bit right-aligned data holding + register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 20 + 12 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DOR1 + DOR1 + channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + SR + SR + status register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAUDR2 + DAC channel2 DMA underrun + flag + 29 + 1 + + + DMAUDR1 + DAC channel1 DMA underrun + flag + 13 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + FPDS + Flash power down in Stop + mode + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + PLS + PVD level selection + 5 + 3 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + LPDS + Low-power deep sleep + 0 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output + selection ready bit + 14 + 1 + read-write + + + + + + + I2C3 + Inter-integrated circuit + I2C + 0x40005C00 + + 0x0 + 0x400 + registers + + + I2C3_EV + I2C3 event interrupt + 72 + + + I2C3_ER + I2C3 error interrupt + 73 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + ALERT + SMBus alert + 13 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + ENARP + ARP enable + 4 + 1 + + + SMBTYPE + SMBus type + 3 + 1 + + + SMBUS + SMBus mode + 1 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADDMODE + Addressing mode (slave + mode) + 15 + 1 + + + ADD10 + Interface address + 8 + 2 + + + ADD7 + Interface address + 1 + 7 + + + ADD0 + Interface address + 0 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x0000 + + + ADD2 + Interface address + 1 + 7 + + + ENDUAL + Dual addressing mode + enable + 0 + 1 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + SMBALERT + SMBus alert + 15 + 1 + read-write + + + TIMEOUT + Timeout or Tlow error + 14 + 1 + read-write + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + ADD10 + 10-bit header sent (Master + mode) + 3 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + SMBHOST + SMBus host header (Slave + mode) + 6 + 1 + + + SMBDEFAULT + SMBus device default address (Slave + mode) + 5 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + I2C2 + 0x40005800 + + I2C2_EV + I2C2 event interrupt + 33 + + + I2C2_ER + I2C2 error interrupt + 34 + + + + I2C1 + 0x40005400 + + I2C1_EV + I2C1 event interrupt + 31 + + + I2C1_ER + I2C1 error interrupt + 32 + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read + 0000h) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window Watchdog interrupt + 0 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x7F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x7F + + + EWI + Early wakeup interrupt + 9 + 1 + + + WDGTB1 + Timer base + 8 + 1 + + + WDGTB0 + Timer base + 7 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00 + + + EWIF + Early wakeup interrupt + flag + 0 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_WKUP + RTC Wakeup interrupt through the EXTI + line + 3 + + + RTC_Alarm + RTC Alarms (A and B) through EXTI line + interrupt + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x00000000 + + + COE + Calibration output enable + 23 + 1 + + + OSEL + Output selection + 21 + 2 + + + POL + Output polarity + 20 + 1 + + + BKP + Backup + 18 + 1 + + + SUB1H + Subtract 1 hour (winter time + change) + 17 + 1 + + + ADD1H + Add 1 hour (summer time + change) + 16 + 1 + + + TSIE + Time-stamp interrupt + enable + 15 + 1 + + + WUTIE + Wakeup timer interrupt + enable + 14 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + DCE + Coarse digital calibration + enable + 7 + 1 + + + FMT + Hour format + 6 + 1 + + + REFCKON + Reference clock detection enable (50 or + 60 Hz) + 4 + 1 + + + TSEDGE + Time-stamp event active + edge + 3 + 1 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + + + ISR + ISR + initialization and status + register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization + flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + ALRAF + Alarm A flag + 8 + 1 + read-write + + + ALRBF + Alarm B flag + 9 + 1 + read-write + + + WUTF + Wakeup timer flag + 10 + 1 + read-write + + + TSF + Time-stamp flag + 11 + 1 + read-write + + + TSOVF + Time-stamp overflow flag + 12 + 1 + read-write + + + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + TAMPER2 detection flag + 14 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + CALIBR + CALIBR + calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCS + Digital calibration sign + 7 + 1 + + + DC + Digital calibration + 0 + 5 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + UART4 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + UART7 + 0x40007800 + + UART4 + UART4 global interrupt + 52 + + + + UART8 + 0x40007C00 + + UART5 + UART5 global interrupt + 53 + + + + C_ADC + Common ADC registers + ADC + 0x40012300 + + 0x0 + 0x400 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + STRT3 + Regular channel Start flag of ADC + 3 + 20 + 1 + + + JSTRT3 + Injected channel Start flag of ADC + 3 + 19 + 1 + + + JEOC3 + Injected channel end of conversion of + ADC 3 + 18 + 1 + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + AWD3 + Analog watchdog flag of ADC + 3 + 16 + 1 + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + STRT2 + Regular channel Start flag of ADC + 2 + 12 + 1 + + + JSTRT2 + Injected channel Start flag of ADC + 2 + 11 + 1 + + + JEOC2 + Injected channel end of conversion of + ADC 2 + 10 + 1 + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + AWD2 + Analog watchdog flag of ADC + 2 + 8 + 1 + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + + STRT1 + Regular channel Start flag of ADC + 1 + 4 + 1 + + + JSTRT1 + Injected channel Start flag of ADC + 1 + 3 + 1 + + + JEOC1 + Injected channel end of conversion of + ADC 1 + 2 + 1 + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + + AWD1 + Analog watchdog flag of ADC + 1 + 0 + 1 + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + VBATE + VBAT enable + 22 + 1 + + + ADCPRE + ADC prescaler + 16 + 2 + + + DMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + DDS + DMA disable selection for multi-ADC + mode + 13 + 1 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + MULT + Multi ADC mode selection + 0 + 5 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular + conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular + conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + + + TIM8 + 0x40010400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + OC2CE + 15 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + OC1M + 4 + 3 + + + OC1PE + OC1PE + 3 + 1 + + + OC1FE + OC1FE + 2 + 1 + + + CC1S + CC1S + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode 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+ 14 + 3 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DFRF + DFRF + 24 + 1 + + + RSF + RSF + 25 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 1 + + + TPSIE + TPSIE + 1 + 1 + + + TBUIE + TBUIE + 2 + 1 + + + TJTIE + TJTIE + 3 + 1 + + + ROIE + ROIE + 4 + 1 + + + TUIE + TUIE + 5 + 1 + + + RIE + RIE + 6 + 1 + + + RBUIE + RBUIE + 7 + 1 + + + RPSIE + RPSIE + 8 + 1 + + + RWTIE + RWTIE + 9 + 1 + + + ETIE + ETIE + 10 + 1 + + + FBEIE + FBEIE + 13 + 1 + + + ERIE + ERIE + 14 + 1 + + + AISE + AISE + 15 + 1 + + + NISE + NISE + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + MFC + MFC + 0 + 16 + + + OMFC + OMFC + 16 + 1 + + + MFA + MFA + 17 + 11 + + + OFOC + OFOC + 28 + 1 + + + + + DMARSWTR + DMARSWTR + Ethernet DMA receive status watchdog timer + register + 0x24 + 0x20 + read-write + 0x00000000 + + + RSWTC + RSWTC + 0 + 8 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + HTDAP + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + HRDAP + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + HTBAP + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + HRBAP + 0 + 32 + + + + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + CR + Control regidter + 0 + 1 + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host + mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size + register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics + register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics + register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics + register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics + register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics + register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics + register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics + register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register + (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register + (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register + (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register + (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register + (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register + (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register + (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register + (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register + (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register + (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register + (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register + (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register + (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + DOEPCTL1 + DOEPCTL1 + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 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Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + F27R2 + F27R2 + Filter bank 27 register 2 + 0x31C + 0x20 + read-write + 0x00000000 + + + FB0 + Filter bits + 0 + 1 + + + FB1 + Filter bits + 1 + 1 + + + FB2 + Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + CAN2 + 0x40006800 + + CAN2_TX + CAN2 TX interrupts + 63 + + + CAN2_RX0 + CAN2 RX0 interrupts + 64 + + + CAN2_RX1 + CAN2 RX1 interrupts + 65 + + + CAN2_SCE + CAN2 SCE interrupt + 66 + + + + FLASH + FLASH + FLASH + 0x40023C00 + + 0x0 + 0x400 + registers + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000000 + + + LATENCY + Latency + 0 + 3 + read-write + + + PRFTEN + Prefetch enable + 8 + 1 + read-write + + + ICEN + Instruction cache enable + 9 + 1 + read-write + + + DCEN + Data cache enable + 10 + 1 + read-write + + + ICRST + Instruction cache reset + 11 + 1 + write-only + + + DCRST + Data cache reset + 12 + 1 + read-write + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + WRPERR + Write protection error + 4 + 1 + read-write + + + PGAERR + Programming alignment + error + 5 + 1 + read-write + + + PGPERR + Programming parallelism + error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x80000000 + + + PG + Programming + 0 + 1 + + + SER + Sector Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + SNB + Sector number + 3 + 4 + + + PSIZE + Program size + 8 + 2 + + + STRT + Start + 16 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + LOCK + Lock + 31 + 1 + + + + + OPTCR + OPTCR + Flash option control register + 0x14 + 0x20 + read-write + 0x00000014 + + + OPTLOCK + Option lock + 0 + 1 + + + OPTSTRT + Option start + 1 + 1 + + + BOR_LEV + BOR reset Level + 2 + 2 + + + WDG_SW + WDG_SW User option bytes + 5 + 1 + + + nRST_STOP + nRST_STOP User option + bytes + 6 + 1 + + + nRST_STDBY + nRST_STDBY User option + bytes + 7 + 1 + + + RDP + Read protect + 8 + 8 + + + nWRP + Not write protect + 16 + 12 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40013C00 + + 0x0 + 0x400 + registers + + + TAMP_STAMP + Tamper and TimeStamp interrupts through the + EXTI line + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + PR19 + Pending bit 19 + 19 + 1 + + + PR20 + Pending bit 20 + 20 + 1 + + + PR21 + Pending bit 21 + 21 + 1 + + + PR22 + Pending bit 22 + 22 + 1 + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x131 + registers + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out global + interrupt + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In global + interrupt + 75 + + + OTG_HS_WKUP + USB On The Go HS Wakeup through EXTI + interrupt + 76 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA request signal + 30 + 1 + read-only + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_GNPTXFSIZ_Host + OTG_HS_GNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_TX0FSIZ_Peripheral + OTG_HS_TX0FSIZ_Peripheral + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_GNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + I2CPADEN + Enable I2C bus connection for the + external I2C PHY interface + 17 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + VBUS sensing disable + option + 21 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Peripheral + OTG_HS_GRXSTSR_Peripheral + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Peripheral + OTG_HS_GRXSTSP_Peripheral + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR11 + OTG_HS_HCCHAR11 + OTG_HS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MC + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 + OTG_HS_HCSPLT6 + OTG_HS host channel-6 split control + register + 0x1C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT7 + OTG_HS_HCSPLT7 + OTG_HS host channel-7 split control + register + 0x1E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT8 + OTG_HS_HCSPLT8 + OTG_HS host channel-8 split control + register + 0x204 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT9 + OTG_HS_HCSPLT9 + OTG_HS host channel-9 split control + register + 0x224 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT10 + OTG_HS_HCSPLT10 + OTG_HS host channel-10 split control + register + 0x244 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT11 + OTG_HS_HCSPLT11 + OTG_HS host channel-11 split control + register + 0x264 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT0 + OTG_HS_HCINT0 + OTG_HS host channel-11 interrupt + register + 0x108 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT1 + OTG_HS_HCINT1 + OTG_HS host channel-1 interrupt + register + 0x128 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT2 + OTG_HS_HCINT2 + OTG_HS host channel-2 interrupt + register + 0x148 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT3 + OTG_HS_HCINT3 + OTG_HS host channel-3 interrupt + register + 0x168 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT4 + OTG_HS_HCINT4 + OTG_HS host channel-4 interrupt + register + 0x188 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT5 + OTG_HS_HCINT5 + OTG_HS host channel-5 interrupt + register + 0x1A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT6 + OTG_HS_HCINT6 + OTG_HS host channel-6 interrupt + register + 0x1C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT7 + OTG_HS_HCINT7 + OTG_HS host channel-7 interrupt + register + 0x1E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT8 + OTG_HS_HCINT8 + OTG_HS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT9 + OTG_HS_HCINT9 + OTG_HS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT10 + OTG_HS_HCINT10 + OTG_HS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT11 + OTG_HS_HCINT11 + OTG_HS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK0 + OTG_HS_HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK2 + OTG_HS_HCINTMSK2 + OTG_HS host channel-2 interrupt mask + register + 0x14C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPEACHMSK1 + OTG_HS_DIEPEACHMSK1 + OTG_HS device each in endpoint-1 interrupt + register + 0x40 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + OTG_HS_DOEPEACHMSK1 + OTG_HS_DOEPEACHMSK1 + OTG_HS device each OUT endpoint-1 interrupt + register + 0x80 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + OUT packet error mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + BERRM + Bubble error interrupt + mask + 12 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + NYETM + NYET interrupt mask + 14 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-1 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-2 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-3 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-4 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-5 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x351 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable + Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending + Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + SAI1 + Serial audio interface + SAI1 + 0x40015800 + + 0x0 + 0x400 + registers + + + + SAI_ACR1 + SAI_ACR1 + SAI AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKDIV + Master clock divider + 20 + 4 + + + MODE + Audio block mode + 0 + 2 + + + PRTCFG + Protocol configuration + 2 + 2 + + + DS + Data size + 5 + 3 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + CKSTR + Clock strobing edge + 9 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + MONO + Mono mode + 12 + 1 + + + OUTDRIV + Output drive + 13 + 1 + + + SAIAEN + Audio block enable + 16 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + NODIV + No divider + 19 + 1 + + + + + SAI_BCR1 + SAI_BCR1 + SAI BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MODE + Audio block mode + 0 + 2 + + + PRTCFG + Protocol configuration + 2 + 2 + + + DS + Data size + 5 + 3 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + CKSTR + Clock strobing edge + 9 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + MONO + Mono mode + 12 + 1 + + + OUTDRIV + Output drive + 13 + 1 + + + SAIBEN + Audio block enable + 16 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + NODIV + No divider + 19 + 1 + + + MCKDIV + Master clock divider + 20 + 4 + + + + + SAI_ACR2 + SAI_ACR2 + SAI AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000040 + + + FTH + FIFO threshold + 0 + 3 + + + FFLUSH + FIFO flush + 3 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + MUTE + Mute + 5 + 1 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTECNT + Mute counter + 7 + 6 + + + CPL + Complement bit + 13 + 1 + + + COMP + Companding mode + 14 + 2 + + + + + SAI_BCR2 + SAI_BCR2 + SAI BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000040 + + + FTH + FIFO threshold + 0 + 3 + + + FFLUSH + FIFO flush + 3 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + MUTE + Mute + 5 + 1 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTECNT + Mute counter + 7 + 6 + + + CPL + Complement bit + 13 + 1 + + + COMP + Companding mode + 14 + 2 + + + + + SAI_AFRCR + SAI_AFRCR + SAI AFrame configuration + register + 0xC + 0x20 + 0x00000007 + + + FRL + Frame length + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FSDEF + Frame synchronization + definition + 16 + 1 + read-only + + + FSPOL + Frame synchronization + polarity + 17 + 1 + read-write + + + FSOFF + Frame synchronization + offset + 18 + 1 + read-write + + + + + SAI_BFRCR + SAI_BFRCR + SAI BFrame configuration + register + 0x2C + 0x20 + 0x00000007 + + + FRL + Frame length + 0 + 8 + read-write + + + FSALL + Frame synchronization active level + length + 8 + 7 + read-write + + + FSDEF + Frame synchronization + definition + 16 + 1 + read-only + + + FSPOL + Frame synchronization + polarity + 17 + 1 + read-write + + + FSOFF + Frame synchronization + offset + 18 + 1 + read-write + + + + + SAI_ASLOTR + SAI_ASLOTR + SAI ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset + 0 + 5 + + + SLOTSZ + Slot size + 6 + 2 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTEN + Slot enable + 16 + 16 + + + + + SAI_BSLOTR + SAI_BSLOTR + SAI BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + FBOFF + First bit offset + 0 + 5 + + + SLOTSZ + Slot size + 6 + 2 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTEN + Slot enable + 16 + 16 + + + + + SAI_AIM + SAI_AIM + SAI AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + MUTEDETIE + Mute detection interrupt + enable + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + + + SAI_BIM + SAI_BIM + SAI BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + MUTEDETIE + Mute detection interrupt + enable + 1 + 1 + + + WCKCFGIE + Wrong clock configuration interrupt + enable + 2 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + + + SAI_ASR + SAI_ASR + SAI AStatus register + 0x18 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + + FREQ + FIFO request + 3 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + FLTH + FIFO level threshold + 16 + 3 + + + + + SAI_BSR + SAI_BSR + SAI BStatus register + 0x38 + 0x20 + read-only + 0x00000008 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + + FREQ + FIFO request + 3 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + FLTH + FIFO level threshold + 16 + 3 + + + + + SAI_ACLRFR + SAI_ACLRFR + SAI AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + + CMUTEDET + Mute detection flag + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + + + SAI_BCLRFR + SAI_BCLRFR + SAI BClear flag register + 0x3C + 0x20 + read-write + 0x00000000 + + + COVRUDR + Clear overrun / underrun + 0 + 1 + + + CMUTEDET + Mute detection flag + 1 + 1 + + + CWCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + CCNRDY + Clear codec not ready flag + 4 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CLFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + + + SAI_ADR + SAI_ADR + SAI AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + SAI_BDR + SAI_BDR + SAI BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + + + LTDC + LCD-TFT Controller + LTDC + 0x40016800 + + 0x0 + 0x400 + registers + + + LCD_TFT + LTDC global interrupt + 88 + + + LCD_TFT_1 + LTDC global error interrupt + 89 + + + + SSCR + SSCR + Synchronization Size Configuration + Register + 0x8 + 0x20 + read-write + 0x00000000 + + + HSW + Horizontal Synchronization Width (in + units of pixel clock period) + 16 + 10 + + + VSH + Vertical Synchronization Height (in + units of horizontal scan line) + 0 + 11 + + + + + BPCR + BPCR + Back Porch Configuration + Register + 0xC + 0x20 + read-write + 0x00000000 + + + AHBP + Accumulated Horizontal back porch (in + units of pixel clock period) + 16 + 10 + + + AVBP + Accumulated Vertical back porch (in + units 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+ enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS + value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation + flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a + return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for + exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register + (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status + register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control + register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + diff --git a/svd/lm3s6965.svd b/svd/lm3s6965.svd new file mode 100644 index 0000000..77f5c8c --- /dev/null +++ b/svd/lm3s6965.svd @@ -0,0 +1,11111 @@ + + + + LM3S6965 + 7944 + ARM Cortex-M3 Stellaris Device + 8 + 32 + 32 + read-write + 0 + 0 + + + WATCHDOG0 + Register map for WATCHDOG0 peripheral + WATCHDOG + WATCHDOG0 + 0x40000000 + + 0 + 0x00001000 + registers + + + + LOAD + Watchdog Load + 0x00000000 + + + WDT_LOAD + Watchdog Load Value + [31:0] + + + + + VALUE + Watchdog Value + 0x00000004 + + + WDT_VALUE + Watchdog Value + [31:0] + + + + + CTL + Watchdog Control + 0x00000008 + + + WDT_CTL_INTEN + Watchdog Interrupt Enable + [0:0] + + + WDT_CTL_RESEN + Watchdog Reset Enable + [1:1] + + + + + ICR + Watchdog Interrupt Clear + 0x0000000C + write-only + + + WDT_ICR + Watchdog Interrupt Clear + [31:0] + write-only + + + + + RIS + Watchdog Raw Interrupt Status + 0x00000010 + + + WDT_RIS_WDTRIS + Watchdog Raw Interrupt Status + [0:0] + + + + + MIS + Watchdog Masked Interrupt Status + 0x00000014 + + + WDT_MIS_WDTMIS + Watchdog Masked Interrupt Status + [0:0] + + + + + TEST + Watchdog Test + 0x00000418 + + + WDT_TEST_STALL + Watchdog Stall Enable + [8:8] + + + + + LOCK + Watchdog Lock + 0x00000C00 + + + WDT_LOCK + Watchdog Lock + [31:0] + + + WDT_LOCK_UNLOCKED + Unlocked + 0x0 + + + WDT_LOCK_LOCKED + Locked + 0x1 + + + WDT_LOCK_UNLOCK + Unlocks the watchdog timer + 0x1acce551 + + + + + + + + + GPIO_PORTA + Register map for GPIO_PORTA peripheral + GPIO_PORT + GPIO_PORTA + 0x40004000 + + 0 + 0x00001000 + registers + + + + DATA + GPIO Data + 0x000003FC + + + DIR + GPIO Direction + 0x00000400 + + + IS + GPIO Interrupt Sense + 0x00000404 + + + IBE + GPIO Interrupt Both Edges + 0x00000408 + + + IEV + GPIO Interrupt Event + 0x0000040C + + + IM + GPIO Interrupt Mask + 0x00000410 + + + RIS + GPIO Raw Interrupt Status + 0x00000414 + + + MIS + GPIO Masked Interrupt Status + 0x00000418 + + + ICR + GPIO Interrupt Clear + 0x0000041C + write-only + + + AFSEL + GPIO Alternate Function Select + 0x00000420 + + + DR2R + GPIO 2-mA Drive Select + 0x00000500 + + + DR4R + GPIO 4-mA Drive Select + 0x00000504 + + + DR8R + GPIO 8-mA Drive Select + 0x00000508 + + + ODR + GPIO Open Drain Select + 0x0000050C + + + PUR + GPIO Pull-Up Select + 0x00000510 + + + PDR + GPIO Pull-Down Select + 0x00000514 + + + SLR + GPIO Slew Rate Control Select + 0x00000518 + + + DEN + GPIO Digital Enable + 0x0000051C + + + LOCK + GPIO Lock + 0x00000520 + + + GPIO_LOCK + GPIO Lock + [31:0] + + + GPIO_LOCK_UNLOCKED + The GPIOCR register is unlocked and may be modified + 0x0 + + + GPIO_LOCK_LOCKED + The GPIOCR register is locked and may not be modified + 0x1 + + + GPIO_LOCK_KEY + Unlocks the GPIO_CR register + 0x1acce551 + + + + + + + CR + GPIO Commit + 0x00000524 + read-only + + + + + GPIO_PORTB + GPIO_PORTB + 0x40005000 + + + GPIO_PORTC + GPIO_PORTC + 0x40006000 + + + GPIO_PORTD + GPIO_PORTD + 0x40007000 + + + SSI0 + Register map for SSI0 peripheral + SSI + SSI0 + 0x40008000 + + 0 + 0x00001000 + registers + + + + CR0 + SSI Control 0 + 0x00000000 + + + SSI_CR0_DSS + SSI Data Size Select + [3:0] + + + SSI_CR0_DSS_4 + 4-bit data + 0x3 + + + SSI_CR0_DSS_5 + 5-bit data + 0x4 + + + SSI_CR0_DSS_6 + 6-bit data + 0x5 + + + SSI_CR0_DSS_7 + 7-bit data + 0x6 + + + SSI_CR0_DSS_8 + 8-bit data + 0x7 + + + SSI_CR0_DSS_9 + 9-bit data + 0x8 + + + SSI_CR0_DSS_10 + 10-bit data + 0x9 + + + SSI_CR0_DSS_11 + 11-bit data + 0xa + + + SSI_CR0_DSS_12 + 12-bit data + 0xb + + + SSI_CR0_DSS_13 + 13-bit data + 0xc + + + SSI_CR0_DSS_14 + 14-bit data + 0xd + + + SSI_CR0_DSS_15 + 15-bit data + 0xe + + + SSI_CR0_DSS_16 + 16-bit data + 0xf + + + + + SSI_CR0_FRF + SSI Frame Format Select + [5:4] + + + SSI_CR0_FRF_MOTO + Freescale SPI Frame Format + 0x0 + + + SSI_CR0_FRF_TI + Texas Instruments Synchronous Serial Frame Format + 0x1 + + + SSI_CR0_FRF_NMW + MICROWIRE Frame Format + 0x2 + + + + + SSI_CR0_SPO + SSI Serial Clock Polarity + [6:6] + + + SSI_CR0_SPH + SSI Serial Clock Phase + [7:7] + + + SSI_CR0_SCR + SSI Serial Clock Rate + [15:8] + + + + + CR1 + SSI Control 1 + 0x00000004 + + + SSI_CR1_LBM + SSI Loopback Mode + [0:0] + + + SSI_CR1_SSE + SSI Synchronous Serial Port Enable + [1:1] + + + SSI_CR1_MS + SSI Master/Slave Select + [2:2] + + + SSI_CR1_SOD + SSI Slave Mode Output Disable + [3:3] + + + + + DR + SSI Data + 0x00000008 + + + SSI_DR_DATA + SSI Receive/Transmit Data + [15:0] + + + + + SR + SSI Status + 0x0000000C + + + SSI_SR_TFE + SSI Transmit FIFO Empty + [0:0] + + + SSI_SR_TNF + SSI Transmit FIFO Not Full + [1:1] + + + SSI_SR_RNE + SSI Receive FIFO Not Empty + [2:2] + + + SSI_SR_RFF + SSI Receive FIFO Full + [3:3] + + + SSI_SR_BSY + SSI Busy Bit + [4:4] + + + + + CPSR + SSI Clock Prescale + 0x00000010 + + + SSI_CPSR_CPSDVSR + SSI Clock Prescale Divisor + [7:0] + + + + + IM + SSI Interrupt Mask + 0x00000014 + + + SSI_IM_RORIM + SSI Receive Overrun Interrupt Mask + [0:0] + + + SSI_IM_RTIM + SSI Receive Time-Out Interrupt Mask + [1:1] + + + SSI_IM_RXIM + SSI Receive FIFO Interrupt Mask + [2:2] + + + SSI_IM_TXIM + SSI Transmit FIFO Interrupt Mask + [3:3] + + + + + RIS + SSI Raw Interrupt Status + 0x00000018 + + + SSI_RIS_RORRIS + SSI Receive Overrun Raw Interrupt Status + [0:0] + + + SSI_RIS_RTRIS + SSI Receive Time-Out Raw Interrupt Status + [1:1] + + + SSI_RIS_RXRIS + SSI Receive FIFO Raw Interrupt Status + [2:2] + + + SSI_RIS_TXRIS + SSI Transmit FIFO Raw Interrupt Status + [3:3] + + + + + MIS + SSI Masked Interrupt Status + 0x0000001C + + + SSI_MIS_RORMIS + SSI Receive Overrun Masked Interrupt Status + [0:0] + + + SSI_MIS_RTMIS + SSI Receive Time-Out Masked Interrupt Status + [1:1] + + + SSI_MIS_RXMIS + SSI Receive FIFO Masked Interrupt Status + [2:2] + + + SSI_MIS_TXMIS + SSI Transmit FIFO Masked Interrupt Status + [3:3] + + + + + ICR + SSI Interrupt Clear + 0x00000020 + write-only + + + SSI_ICR_RORIC + SSI Receive Overrun Interrupt Clear + [0:0] + write-only + + + SSI_ICR_RTIC + SSI Receive Time-Out Interrupt Clear + [1:1] + write-only + + + + + + + UART0 + Register map for UART0 peripheral + UART + UART0 + 0x4000C000 + + 0 + 0x00001000 + registers + + + + DR + UART Data + 0x00000000 + + + UART_DR_DATA + Data Transmitted or Received + [7:0] + + + UART_DR_FE + UART Framing Error + [8:8] + + + UART_DR_PE + UART Parity Error + [9:9] + + + UART_DR_BE + UART Break Error + [10:10] + + + UART_DR_OE + UART Overrun Error + [11:11] + + + + + RSR + UART Receive Status/Error Clear + 0x00000004 + + + UART_RSR_FE + UART Framing Error + [0:0] + + + UART_RSR_PE + UART Parity Error + [1:1] + + + UART_RSR_BE + UART Break Error + [2:2] + + + UART_RSR_OE + UART Overrun Error + [3:3] + + + + + ECR + UART Receive Status/Error Clear + UART_ALT + 0x00000004 + + + UART_ECR_DATA + Error Clear + [7:0] + + + + + FR + UART Flag + 0x00000018 + + + UART_FR_BUSY + UART Busy + [3:3] + + + UART_FR_RXFE + UART Receive FIFO Empty + [4:4] + + + UART_FR_TXFF + UART Transmit FIFO Full + [5:5] + + + UART_FR_RXFF + UART Receive FIFO Full + [6:6] + + + UART_FR_TXFE + UART Transmit FIFO Empty + [7:7] + + + + + ILPR + UART IrDA Low-Power Register + 0x00000020 + + + UART_ILPR_ILPDVSR + IrDA Low-Power Divisor + [7:0] + + + + + IBRD + UART Integer Baud-Rate Divisor + 0x00000024 + + + UART_IBRD_DIVINT + Integer Baud-Rate Divisor + [15:0] + + + + + FBRD + UART Fractional Baud-Rate Divisor + 0x00000028 + + + UART_FBRD_DIVFRAC + Fractional Baud-Rate Divisor + [5:0] + + + + + LCRH + UART Line Control + 0x0000002C + + + UART_LCRH_BRK + UART Send Break + [0:0] + + + UART_LCRH_PEN + UART Parity Enable + [1:1] + + + UART_LCRH_EPS + UART Even Parity Select + [2:2] + + + UART_LCRH_STP2 + UART Two Stop Bits Select + [3:3] + + + UART_LCRH_FEN + UART Enable FIFOs + [4:4] + + + UART_LCRH_WLEN + UART Word Length + [6:5] + + + UART_LCRH_WLEN_5 + 5 bits (default) + 0x0 + + + UART_LCRH_WLEN_6 + 6 bits + 0x1 + + + UART_LCRH_WLEN_7 + 7 bits + 0x2 + + + UART_LCRH_WLEN_8 + 8 bits + 0x3 + + + + + UART_LCRH_SPS + UART Stick Parity Select + [7:7] + + + + + CTL + UART Control + 0x00000030 + + + UART_CTL_UARTEN + UART Enable + [0:0] + + + UART_CTL_SIREN + UART SIR Enable + [1:1] + + + UART_CTL_SIRLP + UART SIR Low-Power Mode + [2:2] + + + UART_CTL_LBE + UART Loop Back Enable + [7:7] + + + UART_CTL_TXE + UART Transmit Enable + [8:8] + + + UART_CTL_RXE + UART Receive Enable + [9:9] + + + + + IFLS + UART Interrupt FIFO Level Select + 0x00000034 + + + UART_IFLS_TX + UART Transmit Interrupt FIFO Level Select + [2:0] + + + UART_IFLS_TX1_8 + TX FIFO &lt;= 1/8 full + 0x0 + + + UART_IFLS_TX2_8 + TX FIFO &lt;= 1/4 full + 0x1 + + + UART_IFLS_TX4_8 + TX FIFO &lt;= 1/2 full (default) + 0x2 + + + UART_IFLS_TX6_8 + TX FIFO &lt;= 3/4 full + 0x3 + + + UART_IFLS_TX7_8 + TX FIFO &lt;= 7/8 full + 0x4 + + + + + UART_IFLS_RX + UART Receive Interrupt FIFO Level Select + [5:3] + + + UART_IFLS_RX1_8 + RX FIFO >= 1/8 full + 0x0 + + + UART_IFLS_RX2_8 + RX FIFO >= 1/4 full + 0x1 + + + UART_IFLS_RX4_8 + RX FIFO >= 1/2 full (default) + 0x2 + + + UART_IFLS_RX6_8 + RX FIFO >= 3/4 full + 0x3 + + + UART_IFLS_RX7_8 + RX FIFO >= 7/8 full + 0x4 + + + + + + + IM + UART Interrupt Mask + 0x00000038 + + + UART_IM_RXIM + UART Receive Interrupt Mask + [4:4] + + + UART_IM_TXIM + UART Transmit Interrupt Mask + [5:5] + + + UART_IM_RTIM + UART Receive Time-Out Interrupt Mask + [6:6] + + + UART_IM_FEIM + UART Framing Error Interrupt Mask + [7:7] + + + UART_IM_PEIM + UART Parity Error Interrupt Mask + [8:8] + + + UART_IM_BEIM + UART Break Error Interrupt Mask + [9:9] + + + UART_IM_OEIM + UART Overrun Error Interrupt Mask + [10:10] + + + + + RIS + UART Raw Interrupt Status + 0x0000003C + + + UART_RIS_RXRIS + UART Receive Raw Interrupt Status + [4:4] + + + UART_RIS_TXRIS + UART Transmit Raw Interrupt Status + [5:5] + + + UART_RIS_RTRIS + UART Receive Time-Out Raw Interrupt Status + [6:6] + + + UART_RIS_FERIS + UART Framing Error Raw Interrupt Status + [7:7] + + + UART_RIS_PERIS + UART Parity Error Raw Interrupt Status + [8:8] + + + UART_RIS_BERIS + UART Break Error Raw Interrupt Status + [9:9] + + + UART_RIS_OERIS + UART Overrun Error Raw Interrupt Status + [10:10] + + + + + MIS + UART Masked Interrupt Status + 0x00000040 + + + UART_MIS_RXMIS + UART Receive Masked Interrupt Status + [4:4] + + + UART_MIS_TXMIS + UART Transmit Masked Interrupt Status + [5:5] + + + UART_MIS_RTMIS + UART Receive Time-Out Masked Interrupt Status + [6:6] + + + UART_MIS_FEMIS + UART Framing Error Masked Interrupt Status + [7:7] + + + UART_MIS_PEMIS + UART Parity Error Masked Interrupt Status + [8:8] + + + UART_MIS_BEMIS + UART Break Error Masked Interrupt Status + [9:9] + + + UART_MIS_OEMIS + UART Overrun Error Masked Interrupt Status + [10:10] + + + + + ICR + UART Interrupt Clear + 0x00000044 + write-only + + + UART_ICR_RXIC + Receive Interrupt Clear + [4:4] + write-only + + + UART_ICR_TXIC + Transmit Interrupt Clear + [5:5] + write-only + + + UART_ICR_RTIC + Receive Time-Out Interrupt Clear + [6:6] + write-only + + + UART_ICR_FEIC + Framing Error Interrupt Clear + [7:7] + write-only + + + UART_ICR_PEIC + Parity Error Interrupt Clear + [8:8] + write-only + + + UART_ICR_BEIC + Break Error Interrupt Clear + [9:9] + write-only + + + UART_ICR_OEIC + Overrun Error Interrupt Clear + [10:10] + write-only + + + + + + + UART1 + UART1 + 0x4000D000 + + + UART2 + UART2 + 0x4000E000 + + + I2C0 + Register map for I2C0 peripheral + I2C + I2C0 + 0x40020000 + + 0 + 0x00001000 + registers + + + + MSA + I2C Master Slave Address + 0x00000000 + + + I2C_MSA_RS + Receive not send + [0:0] + + + I2C_MSA_SA + I2C Slave Address + [7:1] + + + + + SOAR + I2C Slave Own Address + 0x00000800 + + + I2C_SOAR_OAR + I2C Slave Own Address + [6:0] + + + + + SCSR + I2C Slave Control/Status + 0x00000804 + + + I2C_SCSR_RREQ + Receive Request + [0:0] + + + I2C_SCSR_TREQ + Transmit Request + [1:1] + + + I2C_SCSR_FBR + First Byte Received + [2:2] + + + + + SCSR + I2C Slave Control/Status + I2C0_ALT + 0x00000804 + + + I2C_SCSR_DA + Device Active + [0:0] + + + + + MCS + I2C Master Control/Status + 0x00000004 + + + I2C_MCS_RUN + I2C Master Enable + [0:0] + + + I2C_MCS_START + Generate START + [1:1] + + + I2C_MCS_ADRACK + Acknowledge Address + [2:2] + + + I2C_MCS_ACK + Data Acknowledge Enable + [3:3] + + + I2C_MCS_ARBLST + Arbitration Lost + [4:4] + + + I2C_MCS_IDLE + I2C Idle + [5:5] + + + I2C_MCS_BUSBSY + Bus Busy + [6:6] + + + + + MCS + I2C Master Control/Status + I2C0_ALT + 0x00000004 + + + I2C_MCS_BUSY + I2C Busy + [0:0] + + + I2C_MCS_ERROR + Error + [1:1] + + + I2C_MCS_STOP + Generate STOP + [2:2] + + + I2C_MCS_DATACK + Acknowledge Data + [3:3] + + + + + SDR + I2C Slave Data + 0x00000808 + + + I2C_SDR_DATA + Data for Transfer + [7:0] + + + + + MDR + I2C Master Data + 0x00000008 + + + I2C_MDR_DATA + Data Transferred + [7:0] + + + + + MTPR + I2C Master Timer Period + 0x0000000C + + + I2C_MTPR_TPR + SCL Clock Period + [6:0] + + + + + SIMR + I2C Slave Interrupt Mask + 0x0000080C + + + I2C_SIMR_DATAIM + Data Interrupt Mask + [0:0] + + + + + SRIS + I2C Slave Raw Interrupt Status + 0x00000810 + + + I2C_SRIS_DATARIS + Data Raw Interrupt Status + [0:0] + + + + + MIMR + I2C Master Interrupt Mask + 0x00000010 + + + I2C_MIMR_IM + Interrupt Mask + [0:0] + + + + + MRIS + I2C Master Raw Interrupt Status + 0x00000014 + + + I2C_MRIS_RIS + Raw Interrupt Status + [0:0] + + + + + SMIS + I2C Slave Masked Interrupt Status + 0x00000814 + + + I2C_SMIS_DATAMIS + Data Masked Interrupt Status + [0:0] + + + + + SICR + I2C Slave Interrupt Clear + 0x00000818 + write-only + + + I2C_SICR_DATAIC + Data Interrupt Clear + [0:0] + write-only + + + + + MMIS + I2C Master Masked Interrupt Status + 0x00000018 + + + I2C_MMIS_MIS + Masked Interrupt Status + [0:0] + + + + + MICR + I2C Master Interrupt Clear + 0x0000001C + write-only + + + I2C_MICR_IC + Interrupt Clear + [0:0] + write-only + + + + + MCR + I2C Master Configuration + 0x00000020 + + + I2C_MCR_LPBK + I2C Loopback + [0:0] + + + I2C_MCR_MFE + I2C Master Function Enable + [4:4] + + + I2C_MCR_SFE + I2C Slave Function Enable + [5:5] + + + + + + + I2C1 + I2C1 + 0x40021000 + + + GPIO_PORTE + GPIO_PORTE + 0x40024000 + + + GPIO_PORTF + GPIO_PORTF + 0x40025000 + + + GPIO_PORTG + GPIO_PORTG + 0x40026000 + + + PWM0 + Register map for PWM0 peripheral + PWM + PWM0 + 0x40028000 + + 0 + 0x00001000 + registers + + + + CTL + PWM Master Control + 0x00000000 + + + PWM_CTL_GLOBALSYNC0 + Update PWM Generator 0 + [0:0] + + + PWM_CTL_GLOBALSYNC1 + Update PWM Generator 1 + [1:1] + + + PWM_CTL_GLOBALSYNC2 + Update PWM Generator 2 + [2:2] + + + + + SYNC + PWM Time Base Sync + 0x00000004 + + + PWM_SYNC_SYNC0 + Reset Generator 0 Counter + [0:0] + + + PWM_SYNC_SYNC1 + Reset Generator 1 Counter + [1:1] + + + PWM_SYNC_SYNC2 + Reset Generator 2 Counter + [2:2] + + + + + ENABLE + PWM Output Enable + 0x00000008 + + + PWM_ENABLE_PWM0EN + PWM0 Output Enable + [0:0] + + + PWM_ENABLE_PWM1EN + PWM1 Output Enable + [1:1] + + + PWM_ENABLE_PWM2EN + PWM2 Output Enable + [2:2] + + + PWM_ENABLE_PWM3EN + PWM3 Output Enable + [3:3] + + + PWM_ENABLE_PWM4EN + PWM4 Output Enable + [4:4] + + + PWM_ENABLE_PWM5EN + PWM5 Output Enable + [5:5] + + + + + INVERT + PWM Output Inversion + 0x0000000C + + + PWM_INVERT_PWM0INV + Invert PWM0 Signal + [0:0] + + + PWM_INVERT_PWM1INV + Invert PWM1 Signal + [1:1] + + + PWM_INVERT_PWM2INV + Invert PWM2 Signal + [2:2] + + + PWM_INVERT_PWM3INV + Invert PWM3 Signal + [3:3] + + + PWM_INVERT_PWM4INV + Invert PWM4 Signal + [4:4] + + + PWM_INVERT_PWM5INV + Invert PWM5 Signal + [5:5] + + + + + FAULT + PWM Output Fault + 0x00000010 + + + PWM_FAULT_FAULT0 + PWM0 Fault + [0:0] + + + PWM_FAULT_FAULT1 + PWM1 Fault + [1:1] + + + PWM_FAULT_FAULT2 + PWM2 Fault + [2:2] + + + PWM_FAULT_FAULT3 + PWM3 Fault + [3:3] + + + PWM_FAULT_FAULT4 + PWM4 Fault + [4:4] + + + PWM_FAULT_FAULT5 + PWM5 Fault + [5:5] + + + + + INTEN + PWM Interrupt Enable + 0x00000014 + + + PWM_INTEN_INTPWM0 + PWM0 Interrupt Enable + [0:0] + + + PWM_INTEN_INTPWM1 + PWM1 Interrupt Enable + [1:1] + + + PWM_INTEN_INTPWM2 + PWM2 Interrupt Enable + [2:2] + + + PWM_INTEN_INTFAULT + Fault Interrupt Enable + [16:16] + + + + + RIS + PWM Raw Interrupt Status + 0x00000018 + + + PWM_RIS_INTPWM0 + PWM0 Interrupt Asserted + [0:0] + + + PWM_RIS_INTPWM1 + PWM1 Interrupt Asserted + [1:1] + + + PWM_RIS_INTPWM2 + PWM2 Interrupt Asserted + [2:2] + + + PWM_RIS_INTFAULT + Fault Interrupt Asserted + [16:16] + + + + + ISC + PWM Interrupt Status and Clear + 0x0000001C + + + PWM_ISC_INTPWM0 + PWM0 Interrupt Status + [0:0] + + + PWM_ISC_INTPWM1 + PWM1 Interrupt Status + [1:1] + + + PWM_ISC_INTPWM2 + PWM2 Interrupt Status + [2:2] + + + PWM_ISC_INTFAULT + Fault Interrupt Asserted + [16:16] + + + + + STATUS + PWM Status + 0x00000020 + + + _0_CTL + PWM0 Control + 0x00000040 + + + PWM_X_CTL_ENABLE + PWM Block Enable + [0:0] + + + PWM_X_CTL_MODE + Counter Mode + [1:1] + + + PWM_X_CTL_DEBUG + Debug Mode + [2:2] + + + PWM_X_CTL_LOADUPD + Load Register Update Mode + [3:3] + + + PWM_X_CTL_CMPAUPD + Comparator A Update Mode + [4:4] + + + PWM_X_CTL_CMPBUPD + Comparator B Update Mode + [5:5] + + + + + _0_INTEN + PWM0 Interrupt and Trigger Enable + 0x00000044 + + + PWM_X_INTEN_INTCNTZERO + Interrupt for Counter=0 + [0:0] + + + PWM_X_INTEN_INTCNTLOAD + Interrupt for Counter=PWMnLOAD + [1:1] + + + PWM_X_INTEN_INTCMPAU + Interrupt for Counter=PWMnCMPA Up + [2:2] + + + PWM_X_INTEN_INTCMPAD + Interrupt for Counter=PWMnCMPA Down + [3:3] + + + PWM_X_INTEN_INTCMPBU + Interrupt for Counter=PWMnCMPB Up + [4:4] + + + PWM_X_INTEN_INTCMPBD + Interrupt for Counter=PWMnCMPB Down + [5:5] + + + PWM_X_INTEN_TRCNTZERO + Trigger for Counter=0 + [8:8] + + + PWM_X_INTEN_TRCNTLOAD + Trigger for Counter=PWMnLOAD + [9:9] + + + PWM_X_INTEN_TRCMPAU + Trigger for Counter=PWMnCMPA Up + [10:10] + + + PWM_X_INTEN_TRCMPAD + Trigger for Counter=PWMnCMPA Down + [11:11] + + + PWM_X_INTEN_TRCMPBU + Trigger for Counter=PWMnCMPB Up + [12:12] + + + PWM_X_INTEN_TRCMPBD + Trigger for Counter=PWMnCMPB Down + [13:13] + + + + + _0_RIS + PWM0 Raw Interrupt Status + 0x00000048 + + + PWM_X_RIS_INTCNTZERO + Counter=0 Interrupt Status + [0:0] + + + PWM_X_RIS_INTCNTLOAD + Counter=Load Interrupt Status + [1:1] + + + PWM_X_RIS_INTCMPAU + Comparator A Up Interrupt Status + [2:2] + + + PWM_X_RIS_INTCMPAD + Comparator A Down Interrupt Status + [3:3] + + + PWM_X_RIS_INTCMPBU + Comparator B Up Interrupt Status + [4:4] + + + PWM_X_RIS_INTCMPBD + Comparator B Down Interrupt Status + [5:5] + + + + + _0_ISC + PWM0 Interrupt Status and Clear + 0x0000004C + + + PWM_X_ISC_INTCNTZERO + Counter=0 Interrupt + [0:0] + + + PWM_X_ISC_INTCNTLOAD + Counter=Load Interrupt + [1:1] + + + PWM_X_ISC_INTCMPAU + Comparator A Up Interrupt + [2:2] + + + PWM_X_ISC_INTCMPAD + Comparator A Down Interrupt + [3:3] + + + PWM_X_ISC_INTCMPBU + Comparator B Up Interrupt + [4:4] + + + PWM_X_ISC_INTCMPBD + Comparator B Down Interrupt + [5:5] + + + + + _0_LOAD + PWM0 Load + 0x00000050 + + + PWM_X_LOAD + Counter Load Value + [15:0] + + + + + _0_COUNT + PWM0 Counter + 0x00000054 + + + PWM_X_COUNT + Counter Value + [15:0] + + + + + _0_CMPA + PWM0 Compare A + 0x00000058 + + + PWM_X_CMPA + Comparator A Value + [15:0] + + + + + _0_CMPB + PWM0 Compare B + 0x0000005C + + + PWM_X_CMPB + Comparator B Value + [15:0] + + + + + _0_GENA + PWM0 Generator A Control + 0x00000060 + + + PWM_X_GENA_ACTZERO + Action for Counter=0 + [1:0] + + + PWM_X_GENA_ACTZERO_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTZERO_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTZERO_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTZERO_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTLOAD + Action for Counter=LOAD + [3:2] + + + PWM_X_GENA_ACTLOAD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTLOAD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTLOAD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTLOAD_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPAU + Action for Comparator A Up + [5:4] + + + PWM_X_GENA_ACTCMPAU_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPAU_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPAU_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPAU_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPAD + Action for Comparator A Down + [7:6] + + + PWM_X_GENA_ACTCMPAD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPAD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPAD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPAD_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPBU + Action for Comparator B Up + [9:8] + + + PWM_X_GENA_ACTCMPBU_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPBU_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPBU_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPBU_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPBD + Action for Comparator B Down + [11:10] + + + PWM_X_GENA_ACTCMPBD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPBD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPBD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPBD_ONE + Drive pwmA High + 0x3 + + + + + + + _0_GENB + PWM0 Generator B Control + 0x00000064 + + + PWM_X_GENB_ACTZERO + Action for Counter=0 + [1:0] + + + PWM_X_GENB_ACTZERO_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTZERO_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTZERO_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTZERO_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTLOAD + Action for Counter=LOAD + [3:2] + + + PWM_X_GENB_ACTLOAD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTLOAD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTLOAD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTLOAD_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPAU + Action for Comparator A Up + [5:4] + + + PWM_X_GENB_ACTCMPAU_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPAU_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPAU_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPAU_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPAD + Action for Comparator A Down + [7:6] + + + PWM_X_GENB_ACTCMPAD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPAD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPAD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPAD_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPBU + Action for Comparator B Up + [9:8] + + + PWM_X_GENB_ACTCMPBU_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPBU_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPBU_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPBU_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPBD + Action for Comparator B Down + [11:10] + + + PWM_X_GENB_ACTCMPBD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPBD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPBD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPBD_ONE + Drive pwmB High + 0x3 + + + + + + + _0_DBCTL + PWM0 Dead-Band Control + 0x00000068 + + + PWM_X_DBCTL_ENABLE + Dead-Band Generator Enable + [0:0] + + + + + _0_DBRISE + PWM0 Dead-Band Rising-Edge Delay + 0x0000006C + + + PWM_X_DBRISE_DELAY + Dead-Band Rise Delay + [11:0] + + + + + _0_DBFALL + PWM0 Dead-Band Falling-Edge-Delay + 0x00000070 + + + PWM_X_DBFALL_DELAY + Dead-Band Fall Delay + [11:0] + + + + + _1_CTL + PWM1 Control + 0x00000080 + + + _1_INTEN + PWM1 Interrupt and Trigger Enable + 0x00000084 + + + _1_RIS + PWM1 Raw Interrupt Status + 0x00000088 + + + _1_ISC + PWM1 Interrupt Status and Clear + 0x0000008C + + + _1_LOAD + PWM1 Load + 0x00000090 + + + _1_COUNT + PWM1 Counter + 0x00000094 + + + _1_CMPA + PWM1 Compare A + 0x00000098 + + + _1_CMPB + PWM1 Compare B + 0x0000009C + + + _1_GENA + PWM1 Generator A Control + 0x000000A0 + + + _1_GENB + PWM1 Generator B Control + 0x000000A4 + + + _1_DBCTL + PWM1 Dead-Band Control + 0x000000A8 + + + _1_DBRISE + PWM1 Dead-Band Rising-Edge Delay + 0x000000AC + + + _1_DBFALL + PWM1 Dead-Band Falling-Edge-Delay + 0x000000B0 + + + _2_CTL + PWM2 Control + 0x000000C0 + + + _2_INTEN + PWM2 Interrupt and Trigger Enable + 0x000000C4 + + + _2_RIS + PWM2 Raw Interrupt Status + 0x000000C8 + + + _2_ISC + PWM2 Interrupt Status and Clear + 0x000000CC + + + _2_LOAD + PWM2 Load + 0x000000D0 + + + _2_COUNT + PWM2 Counter + 0x000000D4 + + + _2_CMPA + PWM2 Compare A + 0x000000D8 + + + _2_CMPB + PWM2 Compare B + 0x000000DC + + + _2_GENA + PWM2 Generator A Control + 0x000000E0 + + + _2_GENB + PWM2 Generator B Control + 0x000000E4 + + + _2_DBCTL + PWM2 Dead-Band Control + 0x000000E8 + + + _2_DBRISE + PWM2 Dead-Band Rising-Edge Delay + 0x000000EC + + + _2_DBFALL + PWM2 Dead-Band Falling-Edge-Delay + 0x000000F0 + + + + + QEI0 + Register map for QEI0 peripheral + QEI + QEI0 + 0x4002C000 + + 0 + 0x00001000 + registers + + + + CTL + QEI Control + 0x00000000 + + + QEI_CTL_ENABLE + Enable QEI + [0:0] + + + QEI_CTL_SWAP + Swap Signals + [1:1] + + + QEI_CTL_SIGMODE + Signal Mode + [2:2] + + + QEI_CTL_CAPMODE + Capture Mode + [3:3] + + + QEI_CTL_RESMODE + Reset Mode + [4:4] + + + QEI_CTL_VELEN + Capture Velocity + [5:5] + + + QEI_CTL_VELDIV + Predivide Velocity + [8:6] + + + QEI_CTL_VELDIV_1 + QEI clock /1 + 0x0 + + + QEI_CTL_VELDIV_2 + QEI clock /2 + 0x1 + + + QEI_CTL_VELDIV_4 + QEI clock /4 + 0x2 + + + QEI_CTL_VELDIV_8 + QEI clock /8 + 0x3 + + + QEI_CTL_VELDIV_16 + QEI clock /16 + 0x4 + + + QEI_CTL_VELDIV_32 + QEI clock /32 + 0x5 + + + QEI_CTL_VELDIV_64 + QEI clock /64 + 0x6 + + + QEI_CTL_VELDIV_128 + QEI clock /128 + 0x7 + + + + + QEI_CTL_INVA + Invert PhA + [9:9] + + + QEI_CTL_INVB + Invert PhB + [10:10] + + + QEI_CTL_INVI + Invert Index Pulse + [11:11] + + + QEI_CTL_STALLEN + Stall QEI + [12:12] + + + + + STAT + QEI Status + 0x00000004 + + + QEI_STAT_ERROR + Error Detected + [0:0] + + + QEI_STAT_DIRECTION + Direction of Rotation + [1:1] + + + + + POS + QEI Position + 0x00000008 + + + QEI_POS + Current Position Integrator Value + [31:0] + + + + + MAXPOS + QEI Maximum Position + 0x0000000C + + + QEI_MAXPOS + Maximum Position Integrator Value + [31:0] + + + + + LOAD + QEI Timer Load + 0x00000010 + + + QEI_LOAD + Velocity Timer Load Value + [31:0] + + + + + TIME + QEI Timer + 0x00000014 + + + QEI_TIME + Velocity Timer Current Value + [31:0] + + + + + COUNT + QEI Velocity Counter + 0x00000018 + + + QEI_COUNT + Velocity Pulse Count + [31:0] + + + + + SPEED + QEI Velocity + 0x0000001C + + + QEI_SPEED + Velocity + [31:0] + + + + + INTEN + QEI Interrupt Enable + 0x00000020 + + + QEI_INTEN_INDEX + Index Pulse Detected Interrupt Enable + [0:0] + + + QEI_INTEN_TIMER + Timer Expires Interrupt Enable + [1:1] + + + QEI_INTEN_DIR + Direction Change Interrupt Enable + [2:2] + + + QEI_INTEN_ERROR + Phase Error Interrupt Enable + [3:3] + + + + + RIS + QEI Raw Interrupt Status + 0x00000024 + + + QEI_RIS_INDEX + Index Pulse Asserted + [0:0] + + + QEI_RIS_TIMER + Velocity Timer Expired + [1:1] + + + QEI_RIS_DIR + Direction Change Detected + [2:2] + + + QEI_RIS_ERROR + Phase Error Detected + [3:3] + + + + + ISC + QEI Interrupt Status and Clear + 0x00000028 + + + QEI_ISC_INDEX + Index Pulse Interrupt + [0:0] + + + QEI_ISC_TIMER + Velocity Timer Expired Interrupt + [1:1] + + + QEI_ISC_DIR + Direction Change Interrupt + [2:2] + + + QEI_ISC_ERROR + Phase Error Interrupt + [3:3] + + + + + + + QEI1 + QEI1 + 0x4002D000 + + + TIMER0 + Register map for TIMER0 peripheral + TIMER + TIMER0 + 0x40030000 + + 0 + 0x00001000 + registers + + + + CFG + GPTM Configuration + 0x00000000 + + + TIMER_CFG + GPTM Configuration + [2:0] + + + TIMER_CFG_32_BIT_TIMER + 32-bit timer configuration + 0x0 + + + TIMER_CFG_32_BIT_RTC + 32-bit real-time clock (RTC) counter configuration + 0x1 + + + TIMER_CFG_16_BIT + 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR + 0x4 + + + + + + + TAMR + GPTM Timer A Mode + 0x00000004 + + + TIMER_TAMR_TAMR + GPTM Timer A Mode + [1:0] + + + TIMER_TAMR_TAMR_1_SHOT + One-Shot Timer mode + 0x1 + + + TIMER_TAMR_TAMR_PERIOD + Periodic Timer mode + 0x2 + + + TIMER_TAMR_TAMR_CAP + Capture mode + 0x3 + + + + + TIMER_TAMR_TACMR + GPTM Timer A Capture Mode + [2:2] + + + TIMER_TAMR_TAAMS + GPTM Timer A Alternate Mode Select + [3:3] + + + + + TBMR + GPTM Timer B Mode + 0x00000008 + + + TIMER_TBMR_TBMR + GPTM Timer B Mode + [1:0] + + + TIMER_TBMR_TBMR_1_SHOT + One-Shot Timer mode + 0x1 + + + TIMER_TBMR_TBMR_PERIOD + Periodic Timer mode + 0x2 + + + TIMER_TBMR_TBMR_CAP + Capture mode + 0x3 + + + + + TIMER_TBMR_TBCMR + GPTM Timer B Capture Mode + [2:2] + + + TIMER_TBMR_TBAMS + GPTM Timer B Alternate Mode Select + [3:3] + + + + + CTL + GPTM Control + 0x0000000C + + + TIMER_CTL_TAEN + GPTM Timer A Enable + [0:0] + + + TIMER_CTL_TASTALL + GPTM Timer A Stall Enable + [1:1] + + + TIMER_CTL_TAEVENT + GPTM Timer A Event Mode + [3:2] + + + TIMER_CTL_TAEVENT_POS + Positive edge + 0x0 + + + TIMER_CTL_TAEVENT_NEG + Negative edge + 0x1 + + + TIMER_CTL_TAEVENT_BOTH + Both edges + 0x3 + + + + + TIMER_CTL_RTCEN + GPTM RTC Enable + [4:4] + + + TIMER_CTL_TAOTE + GPTM Timer A Output Trigger Enable + [5:5] + + + TIMER_CTL_TAPWML + GPTM Timer A PWM Output Level + [6:6] + + + TIMER_CTL_TBEN + GPTM Timer B Enable + [8:8] + + + TIMER_CTL_TBSTALL + GPTM Timer B Stall Enable + [9:9] + + + TIMER_CTL_TBEVENT + GPTM Timer B Event Mode + [11:10] + + + TIMER_CTL_TBEVENT_POS + Positive edge + 0x0 + + + TIMER_CTL_TBEVENT_NEG + Negative edge + 0x1 + + + TIMER_CTL_TBEVENT_BOTH + Both edges + 0x3 + + + + + TIMER_CTL_TBOTE + GPTM Timer B Output Trigger Enable + [13:13] + + + TIMER_CTL_TBPWML + GPTM Timer B PWM Output Level + [14:14] + + + + + IMR + GPTM Interrupt Mask + 0x00000018 + + + TIMER_IMR_TATOIM + GPTM Timer A Time-Out Interrupt Mask + [0:0] + + + TIMER_IMR_CAMIM + GPTM Capture A Match Interrupt Mask + [1:1] + + + TIMER_IMR_CAEIM + GPTM Capture A Event Interrupt Mask + [2:2] + + + TIMER_IMR_RTCIM + GPTM RTC Interrupt Mask + [3:3] + + + TIMER_IMR_TBTOIM + GPTM Timer B Time-Out Interrupt Mask + [8:8] + + + TIMER_IMR_CBMIM + GPTM Capture B Match Interrupt Mask + [9:9] + + + TIMER_IMR_CBEIM + GPTM Capture B Event Interrupt Mask + [10:10] + + + + + RIS + GPTM Raw Interrupt Status + 0x0000001C + + + TIMER_RIS_TATORIS + GPTM Timer A Time-Out Raw Interrupt + [0:0] + + + TIMER_RIS_CAMRIS + GPTM Capture A Match Raw Interrupt + [1:1] + + + TIMER_RIS_CAERIS + GPTM Capture A Event Raw Interrupt + [2:2] + + + TIMER_RIS_RTCRIS + GPTM RTC Raw Interrupt + [3:3] + + + TIMER_RIS_TBTORIS + GPTM Timer B Time-Out Raw Interrupt + [8:8] + + + TIMER_RIS_CBMRIS + GPTM Capture B Match Raw Interrupt + [9:9] + + + TIMER_RIS_CBERIS + GPTM Capture B Event Raw Interrupt + [10:10] + + + + + MIS + GPTM Masked Interrupt Status + 0x00000020 + + + TIMER_MIS_TATOMIS + GPTM Timer A Time-Out Masked Interrupt + [0:0] + + + TIMER_MIS_CAMMIS + GPTM Capture A Match Masked Interrupt + [1:1] + + + TIMER_MIS_CAEMIS + GPTM Capture A Event Masked Interrupt + [2:2] + + + TIMER_MIS_RTCMIS + GPTM RTC Masked Interrupt + [3:3] + + + TIMER_MIS_TBTOMIS + GPTM Timer B Time-Out Masked Interrupt + [8:8] + + + TIMER_MIS_CBMMIS + GPTM Capture B Match Masked Interrupt + [9:9] + + + TIMER_MIS_CBEMIS + GPTM Capture B Event Masked Interrupt + [10:10] + + + + + ICR + GPTM Interrupt Clear + 0x00000024 + write-only + + + TIMER_ICR_TATOCINT + GPTM Timer A Time-Out Raw Interrupt + [0:0] + write-only + + + TIMER_ICR_CAMCINT + GPTM Capture A Match Interrupt Clear + [1:1] + write-only + + + TIMER_ICR_CAECINT + GPTM Capture A Event Interrupt Clear + [2:2] + write-only + + + TIMER_ICR_RTCCINT + GPTM RTC Interrupt Clear + [3:3] + write-only + + + TIMER_ICR_TBTOCINT + GPTM Timer B Time-Out Interrupt Clear + [8:8] + write-only + + + TIMER_ICR_CBMCINT + GPTM Capture B Match Interrupt Clear + [9:9] + write-only + + + TIMER_ICR_CBECINT + GPTM Capture B Event Interrupt Clear + [10:10] + write-only + + + + + TAILR + GPTM Timer A Interval Load + 0x00000028 + + + TIMER_TAILR_TAILRL + GPTM Timer A Interval Load Register Low + [15:0] + + + TIMER_TAILR_TAILRH + GPTM Timer A Interval Load Register High + [31:16] + + + + + TBILR + GPTM Timer B Interval Load + 0x0000002C + + + TIMER_TBILR_TBILRL + GPTM Timer B Interval Load Register + [15:0] + + + + + TAMATCHR + GPTM Timer A Match + 0x00000030 + + + TIMER_TAMATCHR_TAMRL + GPTM Timer A Match Register Low + [15:0] + + + TIMER_TAMATCHR_TAMRH + GPTM Timer A Match Register High + [31:16] + + + + + TBMATCHR + GPTM Timer B Match + 0x00000034 + + + TIMER_TBMATCHR_TBMRL + GPTM Timer B Match Register Low + [15:0] + + + + + TAPR + GPTM Timer A Prescale + 0x00000038 + + + TIMER_TAPR_TAPSR + GPTM Timer A Prescale + [7:0] + + + + + TBPR + GPTM Timer B Prescale + 0x0000003C + + + TIMER_TBPR_TBPSR + GPTM Timer B Prescale + [7:0] + + + + + TAPMR + GPTM TimerA Prescale Match + 0x00000040 + + + TIMER_TAPMR_TAPSMR + GPTM TimerA Prescale Match + [7:0] + + + + + TBPMR + GPTM TimerB Prescale Match + 0x00000044 + + + TIMER_TBPMR_TBPSMR + GPTM TimerB Prescale Match + [7:0] + + + + + TAR + GPTM Timer A + 0x00000048 + + + TIMER_TAR_TARL + GPTM Timer A Register Low + [15:0] + + + TIMER_TAR_TARH + GPTM Timer A Register High + [31:16] + + + + + TBR + GPTM Timer B + 0x0000004C + + + TIMER_TBR_TBRL + GPTM Timer B + [15:0] + + + + + + + TIMER1 + TIMER1 + 0x40031000 + + + TIMER2 + TIMER2 + 0x40032000 + + + TIMER3 + TIMER3 + 0x40033000 + + + ADC0 + Register map for ADC0 peripheral + ADC + ADC0 + 0x40038000 + + 0 + 0x00001000 + registers + + + + ACTSS + ADC Active Sample Sequencer + 0x00000000 + + + ADC_ACTSS_ASEN0 + ADC SS0 Enable + [0:0] + + + ADC_ACTSS_ASEN1 + ADC SS1 Enable + [1:1] + + + ADC_ACTSS_ASEN2 + ADC SS2 Enable + [2:2] + + + ADC_ACTSS_ASEN3 + ADC SS3 Enable + [3:3] + + + + + RIS + ADC Raw Interrupt Status + 0x00000004 + + + ADC_RIS_INR0 + SS0 Raw Interrupt Status + [0:0] + + + ADC_RIS_INR1 + SS1 Raw Interrupt Status + [1:1] + + + ADC_RIS_INR2 + SS2 Raw Interrupt Status + [2:2] + + + ADC_RIS_INR3 + SS3 Raw Interrupt Status + [3:3] + + + + + IM + ADC Interrupt Mask + 0x00000008 + + + ADC_IM_MASK0 + SS0 Interrupt Mask + [0:0] + + + ADC_IM_MASK1 + SS1 Interrupt Mask + [1:1] + + + ADC_IM_MASK2 + SS2 Interrupt Mask + [2:2] + + + ADC_IM_MASK3 + SS3 Interrupt Mask + [3:3] + + + + + ISC + ADC Interrupt Status and Clear + 0x0000000C + + + ADC_ISC_IN0 + SS0 Interrupt Status and Clear + [0:0] + + + ADC_ISC_IN1 + SS1 Interrupt Status and Clear + [1:1] + + + ADC_ISC_IN2 + SS2 Interrupt Status and Clear + [2:2] + + + ADC_ISC_IN3 + SS3 Interrupt Status and Clear + [3:3] + + + + + OSTAT + ADC Overflow Status + 0x00000010 + + + ADC_OSTAT_OV0 + SS0 FIFO Overflow + [0:0] + + + ADC_OSTAT_OV1 + SS1 FIFO Overflow + [1:1] + + + ADC_OSTAT_OV2 + SS2 FIFO Overflow + [2:2] + + + ADC_OSTAT_OV3 + SS3 FIFO Overflow + [3:3] + + + + + EMUX + ADC Event Multiplexer Select + 0x00000014 + + + ADC_EMUX_EM0 + SS0 Trigger Select + [3:0] + + + ADC_EMUX_EM0_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM0_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM0_COMP1 + Analog Comparator 1 + 0x2 + + + ADC_EMUX_EM0_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM0_TIMER + Timer + 0x5 + + + ADC_EMUX_EM0_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM0_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM0_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM0_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM1 + SS1 Trigger Select + [7:4] + + + ADC_EMUX_EM1_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM1_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM1_COMP1 + Analog Comparator 1 + 0x2 + + + ADC_EMUX_EM1_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM1_TIMER + Timer + 0x5 + + + ADC_EMUX_EM1_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM1_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM1_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM1_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM2 + SS2 Trigger Select + [11:8] + + + ADC_EMUX_EM2_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM2_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM2_COMP1 + Analog Comparator 1 + 0x2 + + + ADC_EMUX_EM2_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM2_TIMER + Timer + 0x5 + + + ADC_EMUX_EM2_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM2_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM2_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM2_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM3 + SS3 Trigger Select + [15:12] + + + ADC_EMUX_EM3_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM3_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM3_COMP1 + Analog Comparator 1 + 0x2 + + + ADC_EMUX_EM3_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM3_TIMER + Timer + 0x5 + + + ADC_EMUX_EM3_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM3_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM3_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM3_ALWAYS + Always (continuously sample) + 0xf + + + + + + + USTAT + ADC Underflow Status + 0x00000018 + + + ADC_USTAT_UV0 + SS0 FIFO Underflow + [0:0] + + + ADC_USTAT_UV1 + SS1 FIFO Underflow + [1:1] + + + ADC_USTAT_UV2 + SS2 FIFO Underflow + [2:2] + + + ADC_USTAT_UV3 + SS3 FIFO Underflow + [3:3] + + + + + SSPRI + ADC Sample Sequencer Priority + 0x00000020 + + + ADC_SSPRI_SS0 + SS0 Priority + [1:0] + + + ADC_SSPRI_SS0_1ST + First priority + 0x0 + + + ADC_SSPRI_SS0_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS0_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS0_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS1 + SS1 Priority + [5:4] + + + ADC_SSPRI_SS1_1ST + First priority + 0x0 + + + ADC_SSPRI_SS1_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS1_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS1_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS2 + SS2 Priority + [9:8] + + + ADC_SSPRI_SS2_1ST + First priority + 0x0 + + + ADC_SSPRI_SS2_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS2_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS2_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS3 + SS3 Priority + [13:12] + + + ADC_SSPRI_SS3_1ST + First priority + 0x0 + + + ADC_SSPRI_SS3_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS3_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS3_4TH + Fourth priority + 0x3 + + + + + + + PSSI + ADC Processor Sample Sequence Initiate + 0x00000028 + + + ADC_PSSI_SS0 + SS0 Initiate + [0:0] + + + ADC_PSSI_SS1 + SS1 Initiate + [1:1] + + + ADC_PSSI_SS2 + SS2 Initiate + [2:2] + + + ADC_PSSI_SS3 + SS3 Initiate + [3:3] + + + + + SAC + ADC Sample Averaging Control + 0x00000030 + + + ADC_SAC_AVG + Hardware Averaging Control + [2:0] + + + ADC_SAC_AVG_OFF + No hardware oversampling + 0x0 + + + ADC_SAC_AVG_2X + 2x hardware oversampling + 0x1 + + + ADC_SAC_AVG_4X + 4x hardware oversampling + 0x2 + + + ADC_SAC_AVG_8X + 8x hardware oversampling + 0x3 + + + ADC_SAC_AVG_16X + 16x hardware oversampling + 0x4 + + + ADC_SAC_AVG_32X + 32x hardware oversampling + 0x5 + + + ADC_SAC_AVG_64X + 64x hardware oversampling + 0x6 + + + + + + + SSMUX0 + ADC Sample Sequence Input Multiplexer Select 0 + 0x00000040 + + + ADC_SSMUX0_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX0_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX0_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX0_MUX3 + 4th Sample Input Select + [13:12] + + + ADC_SSMUX0_MUX4 + 5th Sample Input Select + [17:16] + + + ADC_SSMUX0_MUX5 + 6th Sample Input Select + [21:20] + + + ADC_SSMUX0_MUX6 + 7th Sample Input Select + [25:24] + + + ADC_SSMUX0_MUX7 + 8th Sample Input Select + [29:28] + + + + + SSCTL0 + ADC Sample Sequence Control 0 + 0x00000044 + + + ADC_SSCTL0_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL0_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL0_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL0_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL0_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL0_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL0_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL0_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL0_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL0_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL0_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL0_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL0_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL0_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL0_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL0_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + ADC_SSCTL0_D4 + 5th Sample Diff Input Select + [16:16] + + + ADC_SSCTL0_END4 + 5th Sample is End of Sequence + [17:17] + + + ADC_SSCTL0_IE4 + 5th Sample Interrupt Enable + [18:18] + + + ADC_SSCTL0_TS4 + 5th Sample Temp Sensor Select + [19:19] + + + ADC_SSCTL0_D5 + 6th Sample Diff Input Select + [20:20] + + + ADC_SSCTL0_END5 + 6th Sample is End of Sequence + [21:21] + + + ADC_SSCTL0_IE5 + 6th Sample Interrupt Enable + [22:22] + + + ADC_SSCTL0_TS5 + 6th Sample Temp Sensor Select + [23:23] + + + ADC_SSCTL0_D6 + 7th Sample Diff Input Select + [24:24] + + + ADC_SSCTL0_END6 + 7th Sample is End of Sequence + [25:25] + + + ADC_SSCTL0_IE6 + 7th Sample Interrupt Enable + [26:26] + + + ADC_SSCTL0_TS6 + 7th Sample Temp Sensor Select + [27:27] + + + ADC_SSCTL0_D7 + 8th Sample Diff Input Select + [28:28] + + + ADC_SSCTL0_END7 + 8th Sample is End of Sequence + [29:29] + + + ADC_SSCTL0_IE7 + 8th Sample Interrupt Enable + [30:30] + + + ADC_SSCTL0_TS7 + 8th Sample Temp Sensor Select + [31:31] + + + + + SSFIFO0 + ADC Sample Sequence Result FIFO 0 + 0x00000048 + + + ADC_SSFIFO0_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT0 + ADC Sample Sequence FIFO 0 Status + 0x0000004C + + + ADC_SSFSTAT0_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT0_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT0_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT0_FULL + FIFO Full + [12:12] + + + + + SSMUX1 + ADC Sample Sequence Input Multiplexer Select 1 + 0x00000060 + + + ADC_SSMUX1_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX1_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX1_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX1_MUX3 + 4th Sample Input Select + [13:12] + + + + + SSCTL1 + ADC Sample Sequence Control 1 + 0x00000064 + + + ADC_SSCTL1_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL1_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL1_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL1_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL1_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL1_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL1_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL1_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL1_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL1_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL1_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL1_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL1_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL1_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL1_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL1_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + + + SSFIFO1 + ADC Sample Sequence Result FIFO 1 + 0x00000068 + + + ADC_SSFIFO1_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT1 + ADC Sample Sequence FIFO 1 Status + 0x0000006C + + + ADC_SSFSTAT1_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT1_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT1_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT1_FULL + FIFO Full + [12:12] + + + + + SSMUX2 + ADC Sample Sequence Input Multiplexer Select 2 + 0x00000080 + + + ADC_SSMUX2_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX2_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX2_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX2_MUX3 + 4th Sample Input Select + [13:12] + + + + + SSCTL2 + ADC Sample Sequence Control 2 + 0x00000084 + + + ADC_SSCTL2_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL2_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL2_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL2_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL2_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL2_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL2_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL2_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL2_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL2_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL2_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL2_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL2_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL2_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL2_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL2_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + + + SSFIFO2 + ADC Sample Sequence Result FIFO 2 + 0x00000088 + + + ADC_SSFIFO2_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT2 + ADC Sample Sequence FIFO 2 Status + 0x0000008C + + + ADC_SSFSTAT2_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT2_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT2_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT2_FULL + FIFO Full + [12:12] + + + + + SSMUX3 + ADC Sample Sequence Input Multiplexer Select 3 + 0x000000A0 + + + ADC_SSMUX3_MUX0 + 1st Sample Input Select + [1:0] + + + + + SSCTL3 + ADC Sample Sequence Control 3 + 0x000000A4 + + + ADC_SSCTL3_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL3_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL3_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL3_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + + + SSFIFO3 + ADC Sample Sequence Result FIFO 3 + 0x000000A8 + + + ADC_SSFIFO3_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT3 + ADC Sample Sequence FIFO 3 Status + 0x000000AC + + + ADC_SSFSTAT3_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT3_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT3_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT3_FULL + FIFO Full + [12:12] + + + + + TMLB + ADC Test Mode Loopback + 0x00000100 + + + ADC_TMLB_LB + Loopback Mode Enable + [0:0] + + + + + + + COMP + Register map for COMP peripheral + COMP + COMP + 0x4003C000 + + 0 + 0x00001000 + registers + + + + ACMIS + Analog Comparator Masked Interrupt Status + 0x00000000 + + + COMP_ACMIS_IN0 + Comparator 0 Masked Interrupt Status + [0:0] + + + COMP_ACMIS_IN1 + Comparator 1 Masked Interrupt Status + [1:1] + + + + + ACRIS + Analog Comparator Raw Interrupt Status + 0x00000004 + + + COMP_ACRIS_IN0 + Comparator 0 Interrupt Status + [0:0] + + + COMP_ACRIS_IN1 + Comparator 1 Interrupt Status + [1:1] + + + + + ACINTEN + Analog Comparator Interrupt Enable + 0x00000008 + + + COMP_ACINTEN_IN0 + Comparator 0 Interrupt Enable + [0:0] + + + COMP_ACINTEN_IN1 + Comparator 1 Interrupt Enable + [1:1] + + + + + ACREFCTL + Analog Comparator Reference Voltage Control + 0x00000010 + + + COMP_ACREFCTL_VREF + Resistor Ladder Voltage Ref + [3:0] + + + COMP_ACREFCTL_RNG + Resistor Ladder Range + [8:8] + + + COMP_ACREFCTL_EN + Resistor Ladder Enable + [9:9] + + + + + ACSTAT0 + Analog Comparator Status 0 + 0x00000020 + + + COMP_ACSTAT0_OVAL + Comparator Output Value + [1:1] + + + + + ACCTL0 + Analog Comparator Control 0 + 0x00000024 + + + COMP_ACCTL0_CINV + Comparator Output Invert + [1:1] + + + COMP_ACCTL0_ISEN + Interrupt Sense + [3:2] + + + COMP_ACCTL0_ISEN_LEVEL + Level sense, see ISLVAL + 0x0 + + + COMP_ACCTL0_ISEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL0_ISEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL0_ISEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL0_ISLVAL + Interrupt Sense Level Value + [4:4] + + + COMP_ACCTL0_TSEN + Trigger Sense + [6:5] + + + COMP_ACCTL0_TSEN_LEVEL + Level sense, see TSLVAL + 0x0 + + + COMP_ACCTL0_TSEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL0_TSEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL0_TSEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL0_TSLVAL + Trigger Sense Level Value + [7:7] + + + COMP_ACCTL0_ASRCP + Analog Source Positive + [10:9] + + + COMP_ACCTL0_ASRCP_PIN + Pin value of Cn+ + 0x0 + + + COMP_ACCTL0_ASRCP_PIN0 + Pin value of C0+ + 0x1 + + + COMP_ACCTL0_ASRCP_REF + Internal voltage reference (VIREF) + 0x2 + + + + + COMP_ACCTL0_TOEN + Trigger Output Enable + [11:11] + + + + + ACSTAT1 + Analog Comparator Status 1 + 0x00000040 + + + COMP_ACSTAT1_OVAL + Comparator Output Value + [1:1] + + + + + ACCTL1 + Analog Comparator Control 1 + 0x00000044 + + + COMP_ACCTL1_CINV + Comparator Output Invert + [1:1] + + + COMP_ACCTL1_ISEN + Interrupt Sense + [3:2] + + + COMP_ACCTL1_ISEN_LEVEL + Level sense, see ISLVAL + 0x0 + + + COMP_ACCTL1_ISEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL1_ISEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL1_ISEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL1_ISLVAL + Interrupt Sense Level Value + [4:4] + + + COMP_ACCTL1_TSEN + Trigger Sense + [6:5] + + + COMP_ACCTL1_TSEN_LEVEL + Level sense, see TSLVAL + 0x0 + + + COMP_ACCTL1_TSEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL1_TSEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL1_TSEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL1_TSLVAL + Trigger Sense Level Value + [7:7] + + + COMP_ACCTL1_ASRCP + Analog Source Positive + [10:9] + + + COMP_ACCTL1_ASRCP_PIN + Pin value of Cn+ + 0x0 + + + COMP_ACCTL1_ASRCP_PIN0 + Pin value of C0+ + 0x1 + + + COMP_ACCTL1_ASRCP_REF + Internal voltage reference (VIREF) + 0x2 + + + + + COMP_ACCTL1_TOEN + Trigger Output Enable + [11:11] + + + + + + + MAC + Register map for MAC peripheral + MAC + MAC + 0x40048000 + + 0 + 0x00001000 + registers + + + + RIS + Ethernet MAC Raw Interrupt Status/Acknowledge + 0x00000000 + + + MAC_RIS_RXINT + Packet Received + [0:0] + + + MAC_RIS_TXER + Transmit Error + [1:1] + + + MAC_RIS_TXEMP + Transmit FIFO Empty + [2:2] + + + MAC_RIS_FOV + FIFO Overrun + [3:3] + + + MAC_RIS_RXER + Receive Error + [4:4] + + + MAC_RIS_MDINT + MII Transaction Complete + [5:5] + + + MAC_RIS_PHYINT + PHY Interrupt + [6:6] + + + + + IACK + Ethernet MAC Raw Interrupt Status/Acknowledge + MAC_ALT + 0x00000000 + + + MAC_IACK_RXINT + Clear Packet Received + [0:0] + + + MAC_IACK_TXER + Clear Transmit Error + [1:1] + + + MAC_IACK_TXEMP + Clear Transmit FIFO Empty + [2:2] + + + MAC_IACK_FOV + Clear FIFO Overrun + [3:3] + + + MAC_IACK_RXER + Clear Receive Error + [4:4] + + + MAC_IACK_MDINT + Clear MII Transaction Complete + [5:5] + + + MAC_IACK_PHYINT + Clear PHY Interrupt + [6:6] + + + + + IM + Ethernet MAC Interrupt Mask + 0x00000004 + + + MAC_IM_RXINTM + Mask Packet Received + [0:0] + + + MAC_IM_TXERM + Mask Transmit Error + [1:1] + + + MAC_IM_TXEMPM + Mask Transmit FIFO Empty + [2:2] + + + MAC_IM_FOVM + Mask FIFO Overrun + [3:3] + + + MAC_IM_RXERM + Mask Receive Error + [4:4] + + + MAC_IM_MDINTM + Mask MII Transaction Complete + [5:5] + + + MAC_IM_PHYINTM + Mask PHY Interrupt + [6:6] + + + + + RCTL + Ethernet MAC Receive Control + 0x00000008 + + + MAC_RCTL_RXEN + Enable Receiver + [0:0] + + + MAC_RCTL_AMUL + Enable Multicast Frames + [1:1] + + + MAC_RCTL_PRMS + Enable Promiscuous Mode + [2:2] + + + MAC_RCTL_BADCRC + Enable Reject Bad CRC + [3:3] + + + MAC_RCTL_RSTFIFO + Clear Receive FIFO + [4:4] + + + + + TCTL + Ethernet MAC Transmit Control + 0x0000000C + + + MAC_TCTL_TXEN + Enable Transmitter + [0:0] + + + MAC_TCTL_PADEN + Enable Packet Padding + [1:1] + + + MAC_TCTL_CRC + Enable CRC Generation + [2:2] + + + MAC_TCTL_DUPLEX + Enable Duplex Mode + [4:4] + + + + + DATA + Ethernet MAC Data + 0x00000010 + + + MAC_DATA_RXDATA + Receive FIFO Data + [31:0] + + + + + DATA + Ethernet MAC Data + MAC_ALT + 0x00000010 + + + MAC_DATA_TXDATA + Transmit FIFO Data + [31:0] + + + + + IA0 + Ethernet MAC Individual Address 0 + 0x00000014 + + + MAC_IA0_MACOCT1 + MAC Address Octet 1 + [7:0] + + + MAC_IA0_MACOCT2 + MAC Address Octet 2 + [15:8] + + + MAC_IA0_MACOCT3 + MAC Address Octet 3 + [23:16] + + + MAC_IA0_MACOCT4 + MAC Address Octet 4 + [31:24] + + + + + IA1 + Ethernet MAC Individual Address 1 + 0x00000018 + + + MAC_IA1_MACOCT5 + MAC Address Octet 5 + [7:0] + + + MAC_IA1_MACOCT6 + MAC Address Octet 6 + [15:8] + + + + + THR + Ethernet MAC Threshold + 0x0000001C + + + MAC_THR_THRESH + Threshold Value + [5:0] + + + + + MCTL + Ethernet MAC Management Control + 0x00000020 + + + MAC_MCTL_START + MII Register Transaction Enable + [0:0] + + + MAC_MCTL_WRITE + MII Register Transaction Type + [1:1] + + + MAC_MCTL_REGADR + MII Register Address + [7:3] + + + + + MDV + Ethernet MAC Management Divider + 0x00000024 + + + MAC_MDV_DIV + Clock Divider + [7:0] + + + + + MTXD + Ethernet MAC Management Transmit Data + 0x0000002C + + + MAC_MTXD_MDTX + MII Register Transmit Data + [15:0] + + + + + MRXD + Ethernet MAC Management Receive Data + 0x00000030 + + + MAC_MRXD_MDRX + MII Register Receive Data + [15:0] + + + + + NP + Ethernet MAC Number of Packets + 0x00000034 + + + MAC_NP_NPR + Number of Packets in Receive FIFO + [5:0] + + + + + TR + Ethernet MAC Transmission Request + 0x00000038 + + + MAC_TR_NEWTX + New Transmission + [0:0] + + + + + + + HIB + Register map for HIB peripheral + HIB + HIB + 0x400FC000 + + 0 + 0x00001000 + registers + + + + RTCC + Hibernation RTC Counter + 0x00000000 + + + HIB_RTCC + RTC Counter + [31:0] + + + + + RTCM0 + Hibernation RTC Match 0 + 0x00000004 + + + HIB_RTCM0 + RTC Match 0 + [31:0] + + + + + RTCM1 + Hibernation RTC Match 1 + 0x00000008 + + + HIB_RTCM1 + RTC Match 1 + [31:0] + + + + + RTCLD + Hibernation RTC Load + 0x0000000C + + + HIB_RTCLD + RTC Load + [31:0] + + + + + CTL + Hibernation Control + 0x00000010 + + + HIB_CTL_RTCEN + RTC Timer Enable + [0:0] + + + HIB_CTL_HIBREQ + Hibernation Request + [1:1] + + + HIB_CTL_CLKSEL + Hibernation Module Clock Select + [2:2] + + + HIB_CTL_RTCWEN + RTC Wake-up Enable + [3:3] + + + HIB_CTL_PINWEN + External WAKE Pin Enable + [4:4] + + + HIB_CTL_LOWBATEN + Low Battery Monitoring Enable + [5:5] + + + HIB_CTL_CLK32EN + Clocking Enable + [6:6] + + + HIB_CTL_VABORT + Power Cut Abort Enable + [7:7] + + + + + IM + Hibernation Interrupt Mask + 0x00000014 + + + HIB_IM_RTCALT0 + RTC Alert 0 Interrupt Mask + [0:0] + + + HIB_IM_RTCALT1 + RTC Alert 1 Interrupt Mask + [1:1] + + + HIB_IM_LOWBAT + Low Battery Voltage Interrupt Mask + [2:2] + + + HIB_IM_EXTW + External Wake-Up Interrupt Mask + [3:3] + + + + + RIS + Hibernation Raw Interrupt Status + 0x00000018 + + + HIB_RIS_RTCALT0 + RTC Alert 0 Raw Interrupt Status + [0:0] + + + HIB_RIS_RTCALT1 + RTC Alert 1 Raw Interrupt Status + [1:1] + + + HIB_RIS_LOWBAT + Low Battery Voltage Raw Interrupt Status + [2:2] + + + HIB_RIS_EXTW + External Wake-Up Raw Interrupt Status + [3:3] + + + + + MIS + Hibernation Masked Interrupt Status + 0x0000001C + + + HIB_MIS_RTCALT0 + RTC Alert 0 Masked Interrupt Status + [0:0] + + + HIB_MIS_RTCALT1 + RTC Alert 1 Masked Interrupt Status + [1:1] + + + HIB_MIS_LOWBAT + Low Battery Voltage Masked Interrupt Status + [2:2] + + + HIB_MIS_EXTW + External Wake-Up Masked Interrupt Status + [3:3] + + + + + IC + Hibernation Interrupt Clear + 0x00000020 + + + HIB_IC_RTCALT0 + RTC Alert0 Masked Interrupt Clear + [0:0] + + + HIB_IC_RTCALT1 + RTC Alert1 Masked Interrupt Clear + [1:1] + + + HIB_IC_LOWBAT + Low Battery Voltage Masked Interrupt Clear + [2:2] + + + HIB_IC_EXTW + External Wake-Up Masked Interrupt Clear + [3:3] + + + + + RTCT + Hibernation RTC Trim + 0x00000024 + + + HIB_RTCT_TRIM + RTC Trim Value + [15:0] + + + + + DATA + Hibernation Data + 0x00000030 + + + HIB_DATA_RTD + Hibernation Module NV Data + [31:0] + + + + + + + FLASH_CTRL + Register map for FLASH_CTRL peripheral + FLASH_CTRL + FLASH_CTRL + 0x400FD000 + + 0 + 0x00001000 + registers + + + 0x1000 + 0x00001000 + registers + + + + FMA + Flash Memory Address + 0x00000000 + + + FLASH_FMA_OFFSET + Address Offset + [17:0] + + + + + FMD + Flash Memory Data + 0x00000004 + + + FLASH_FMD_DATA + Data Value + [31:0] + + + + + FMC + Flash Memory Control + 0x00000008 + + + FLASH_FMC_WRITE + Write a Word into Flash Memory + [0:0] + + + FLASH_FMC_ERASE + Erase a Page of Flash Memory + [1:1] + + + FLASH_FMC_MERASE + Mass Erase Flash Memory + [2:2] + + + FLASH_FMC_COMT + Commit Register Value + [3:3] + + + FLASH_FMC_WRKEY + FLASH write key + [31:17] + + + + + FCRIS + Flash Controller Raw Interrupt Status + 0x0000000C + + + FLASH_FCRIS_ARIS + Access Raw Interrupt Status + [0:0] + + + FLASH_FCRIS_PRIS + Programming Raw Interrupt Status + [1:1] + + + + + FCIM + Flash Controller Interrupt Mask + 0x00000010 + + + FLASH_FCIM_AMASK + Access Interrupt Mask + [0:0] + + + FLASH_FCIM_PMASK + Programming Interrupt Mask + [1:1] + + + + + FCMISC + Flash Controller Masked Interrupt Status and Clear + 0x00000014 + + + FLASH_FCMISC_AMISC + Access Masked Interrupt Status and Clear + [0:0] + + + FLASH_FCMISC_PMISC + Programming Masked Interrupt Status and Clear + [1:1] + + + + + USECRL + USec Reload + 0x00001140 + + + FLASH_USECRL + Microsecond Reload Value + [7:0] + + + + + USERDBG + User Debug + FLASH_ALT + 0x000011D0 + + + FLASH_USERDBG_DBG0 + Debug Control 0 + [0:0] + + + FLASH_USERDBG_DBG1 + Debug Control 1 + [1:1] + + + FLASH_USERDBG_DATA + User Data + [30:2] + + + FLASH_USERDBG_NW + User Debug Not Written + [31:31] + + + + + USERREG0 + User Register 0 + 0x000011E0 + + + FLASH_USERREG0_DATA + User Data + [30:0] + + + FLASH_USERREG0_NW + Not Written + [31:31] + + + + + USERREG1 + User Register 1 + 0x000011E4 + + + FLASH_USERREG1_DATA + User Data + [30:0] + + + FLASH_USERREG1_NW + Not Written + [31:31] + + + + + FMPRE0 + Flash Memory Protection Read Enable 0 + 0x00001200 + + + FMPRE1 + Flash Memory Protection Read Enable 1 + 0x00001204 + + + FMPRE2 + Flash Memory Protection Read Enable 2 + 0x00001208 + + + FMPRE3 + Flash Memory Protection Read Enable 3 + 0x0000120C + + + FMPPE0 + Flash Memory Protection Program Enable 0 + 0x00001400 + + + FMPPE1 + Flash Memory Protection Program Enable 1 + 0x00001404 + + + FMPPE2 + Flash Memory Protection Program Enable 2 + 0x00001408 + + + FMPPE3 + Flash Memory Protection Program Enable 3 + 0x0000140C + + + + + SYSCTL + Register map for SYSCTL peripheral + SYSCTL + SYSCTL + 0x400FE000 + + 0 + 0x00001000 + registers + + + + DID0 + Device Identification 0 + 0x00000000 + + + SYSCTL_DID0_MIN + Minor Revision + [7:0] + + + SYSCTL_DID0_MIN_0 + Initial device, or a major revision update + 0x0 + + + SYSCTL_DID0_MIN_1 + First metal layer change + 0x1 + + + SYSCTL_DID0_MIN_2 + Second metal layer change + 0x2 + + + + + SYSCTL_DID0_MAJ + Major Revision + [15:8] + + + SYSCTL_DID0_MAJ_REVA + Revision A (initial device) + 0x0 + + + SYSCTL_DID0_MAJ_REVB + Revision B (first base layer revision) + 0x1 + + + SYSCTL_DID0_MAJ_REVC + Revision C (second base layer revision) + 0x2 + + + + + SYSCTL_DID0_CLASS + Device Class + [23:16] + + + SYSCTL_DID0_CLASS_FURY + Stellaris(R) Fury-class devices + 0x1 + + + + + SYSCTL_DID0_VER + DID0 Version + [30:28] + + + SYSCTL_DID0_VER_1 + Second version of the DID0 register format + 0x1 + + + + + + + DID1 + Device Identification 1 + 0x00000004 + + + SYSCTL_DID1_QUAL + Qualification Status + [1:0] + + + SYSCTL_DID1_QUAL_ES + Engineering Sample (unqualified) + 0x0 + + + SYSCTL_DID1_QUAL_PP + Pilot Production (unqualified) + 0x1 + + + SYSCTL_DID1_QUAL_FQ + Fully Qualified + 0x2 + + + + + SYSCTL_DID1_ROHS + RoHS-Compliance + [2:2] + + + SYSCTL_DID1_PKG + Package Type + [4:3] + + + SYSCTL_DID1_PKG_SOIC + SOIC package + 0x0 + + + SYSCTL_DID1_PKG_QFP + LQFP package + 0x1 + + + SYSCTL_DID1_PKG_BGA + BGA package + 0x2 + + + + + SYSCTL_DID1_TEMP + Temperature Range + [7:5] + + + SYSCTL_DID1_TEMP_C + Commercial temperature range (0C to 70C) + 0x0 + + + SYSCTL_DID1_TEMP_I + Industrial temperature range (-40C to 85C) + 0x1 + + + SYSCTL_DID1_TEMP_E + Extended temperature range (-40C to 105C) + 0x2 + + + + + SYSCTL_DID1_PINCNT + Package Pin Count + [15:13] + + + SYSCTL_DID1_PINCNT_100 + 100-pin package + 0x2 + + + + + SYSCTL_DID1_PRTNO + Part Number + [23:16] + + + SYSCTL_DID1_PRTNO_6965 + LM3S6965 + 0x73 + + + + + SYSCTL_DID1_FAM + Family + [27:24] + + + SYSCTL_DID1_FAM_STELLARIS + Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S + 0x0 + + + + + SYSCTL_DID1_VER + DID1 Version + [31:28] + + + SYSCTL_DID1_VER_1 + Second version of the DID1 register format + 0x1 + + + + + + + DC0 + Device Capabilities 0 + 0x00000008 + + + SYSCTL_DC0_FLASHSZ + Flash Size + [15:0] + + + SYSCTL_DC0_FLASHSZ_256K + 256 KB of Flash + 0x7f + + + + + SYSCTL_DC0_SRAMSZ + SRAM Size + [31:16] + + + SYSCTL_DC0_SRAMSZ_64KB + 64 KB of SRAM + 0xff + + + + + + + DC1 + Device Capabilities 1 + 0x00000010 + + + SYSCTL_DC1_JTAG + JTAG Present + [0:0] + + + SYSCTL_DC1_SWD + SWD Present + [1:1] + + + SYSCTL_DC1_SWO + SWO Trace Port Present + [2:2] + + + SYSCTL_DC1_WDT0 + Watchdog Timer 0 Present + [3:3] + + + SYSCTL_DC1_PLL + PLL Present + [4:4] + + + SYSCTL_DC1_TEMP + Temp Sensor Present + [5:5] + + + SYSCTL_DC1_HIB + Hibernation Module Present + [6:6] + + + SYSCTL_DC1_MPU + MPU Present + [7:7] + + + SYSCTL_DC1_MINSYSDIV + System Clock Divider + [15:12] + + + SYSCTL_DC1_MINSYSDIV_50 + Specifies a 50-MHz CPU clock with a PLL divider of 4 + 0x3 + + + + + + + DC2 + Device Capabilities 2 + 0x00000014 + + + SYSCTL_DC2_UART0 + UART Module 0 Present + [0:0] + + + SYSCTL_DC2_UART1 + UART Module 1 Present + [1:1] + + + SYSCTL_DC2_UART2 + UART Module 2 Present + [2:2] + + + SYSCTL_DC2_SSI0 + SSI Module 0 Present + [4:4] + + + SYSCTL_DC2_QEI0 + QEI Module 0 Present + [8:8] + + + SYSCTL_DC2_QEI1 + QEI Module 1 Present + [9:9] + + + SYSCTL_DC2_I2C0 + I2C Module 0 Present + [12:12] + + + SYSCTL_DC2_I2C1 + I2C Module 1 Present + [14:14] + + + SYSCTL_DC2_TIMER0 + Timer Module 0 Present + [16:16] + + + SYSCTL_DC2_TIMER1 + Timer Module 1 Present + [17:17] + + + SYSCTL_DC2_TIMER2 + Timer Module 2 Present + [18:18] + + + SYSCTL_DC2_TIMER3 + Timer Module 3 Present + [19:19] + + + SYSCTL_DC2_COMP0 + Analog Comparator 0 Present + [24:24] + + + SYSCTL_DC2_COMP1 + Analog Comparator 1 Present + [25:25] + + + + + DC3 + Device Capabilities 3 + 0x00000018 + + + SYSCTL_DC3_PWM0 + PWM0 Pin Present + [0:0] + + + SYSCTL_DC3_PWM1 + PWM1 Pin Present + [1:1] + + + SYSCTL_DC3_PWM2 + PWM2 Pin Present + [2:2] + + + SYSCTL_DC3_PWM3 + PWM3 Pin Present + [3:3] + + + SYSCTL_DC3_PWM4 + PWM4 Pin Present + [4:4] + + + SYSCTL_DC3_PWM5 + PWM5 Pin Present + [5:5] + + + SYSCTL_DC3_C0MINUS + C0- Pin Present + [6:6] + + + SYSCTL_DC3_C0PLUS + C0+ Pin Present + [7:7] + + + SYSCTL_DC3_C0O + C0o Pin Present + [8:8] + + + SYSCTL_DC3_C1MINUS + C1- Pin Present + [9:9] + + + SYSCTL_DC3_C1PLUS + C1+ Pin Present + [10:10] + + + SYSCTL_DC3_PWMFAULT + PWM Fault Pin Present + [15:15] + + + SYSCTL_DC3_CCP0 + CCP0 Pin Present + [24:24] + + + SYSCTL_DC3_CCP1 + CCP1 Pin Present + [25:25] + + + SYSCTL_DC3_CCP2 + CCP2 Pin Present + [26:26] + + + SYSCTL_DC3_CCP3 + CCP3 Pin Present + [27:27] + + + SYSCTL_DC3_32KHZ + 32KHz Input Clock Available + [31:31] + + + + + DC4 + Device Capabilities 4 + 0x0000001C + + + SYSCTL_DC4_GPIOA + GPIO Port A Present + [0:0] + + + SYSCTL_DC4_GPIOB + GPIO Port B Present + [1:1] + + + SYSCTL_DC4_GPIOC + GPIO Port C Present + [2:2] + + + SYSCTL_DC4_GPIOD + GPIO Port D Present + [3:3] + + + SYSCTL_DC4_GPIOE + GPIO Port E Present + [4:4] + + + SYSCTL_DC4_GPIOF + GPIO Port F Present + [5:5] + + + SYSCTL_DC4_GPIOG + GPIO Port G Present + [6:6] + + + SYSCTL_DC4_EMAC0 + Ethernet MAC Layer 0 Present + [28:28] + + + SYSCTL_DC4_EPHY0 + Ethernet PHY Layer 0 Present + [30:30] + + + + + PBORCTL + Brown-Out Reset Control + 0x00000030 + + + SYSCTL_PBORCTL_BORIOR + BOR Interrupt or Reset + [1:1] + + + + + LDOPCTL + LDO Power Control + 0x00000034 + + + SYSCTL_LDOPCTL + LDO Output Voltage + [5:0] + + + SYSCTL_LDOPCTL_2_50V + 2.50 + 0x0 + + + SYSCTL_LDOPCTL_2_45V + 2.45 + 0x1 + + + SYSCTL_LDOPCTL_2_40V + 2.40 + 0x2 + + + SYSCTL_LDOPCTL_2_35V + 2.35 + 0x3 + + + SYSCTL_LDOPCTL_2_30V + 2.30 + 0x4 + + + SYSCTL_LDOPCTL_2_25V + 2.25 + 0x5 + + + SYSCTL_LDOPCTL_2_75V + 2.75 + 0x1b + + + SYSCTL_LDOPCTL_2_70V + 2.70 + 0x1c + + + SYSCTL_LDOPCTL_2_65V + 2.65 + 0x1d + + + SYSCTL_LDOPCTL_2_60V + 2.60 + 0x1e + + + SYSCTL_LDOPCTL_2_55V + 2.55 + 0x1f + + + + + + + SRCR0 + Software Reset Control 0 + 0x00000040 + + + SYSCTL_SRCR0_HIB + HIB Reset Control + [6:6] + + + + + SRCR1 + Software Reset Control 1 + 0x00000044 + + + SYSCTL_SRCR1_UART0 + UART0 Reset Control + [0:0] + + + SYSCTL_SRCR1_UART1 + UART1 Reset Control + [1:1] + + + SYSCTL_SRCR1_UART2 + UART2 Reset Control + [2:2] + + + SYSCTL_SRCR1_SSI0 + SSI0 Reset Control + [4:4] + + + SYSCTL_SRCR1_QEI0 + QEI0 Reset Control + [8:8] + + + SYSCTL_SRCR1_QEI1 + QEI1 Reset Control + [9:9] + + + SYSCTL_SRCR1_I2C0 + I2C0 Reset Control + [12:12] + + + SYSCTL_SRCR1_I2C1 + I2C1 Reset Control + [14:14] + + + SYSCTL_SRCR1_TIMER0 + Timer 0 Reset Control + [16:16] + + + SYSCTL_SRCR1_TIMER1 + Timer 1 Reset Control + [17:17] + + + SYSCTL_SRCR1_TIMER2 + Timer 2 Reset Control + [18:18] + + + SYSCTL_SRCR1_TIMER3 + Timer 3 Reset Control + [19:19] + + + SYSCTL_SRCR1_COMP0 + Analog Comp 0 Reset Control + [24:24] + + + SYSCTL_SRCR1_COMP1 + Analog Comp 1 Reset Control + [25:25] + + + + + SRCR2 + Software Reset Control 2 + 0x00000048 + + + SYSCTL_SRCR2_GPIOA + Port A Reset Control + [0:0] + + + SYSCTL_SRCR2_GPIOB + Port B Reset Control + [1:1] + + + SYSCTL_SRCR2_GPIOC + Port C Reset Control + [2:2] + + + SYSCTL_SRCR2_GPIOD + Port D Reset Control + [3:3] + + + SYSCTL_SRCR2_GPIOE + Port E Reset Control + [4:4] + + + SYSCTL_SRCR2_GPIOF + Port F Reset Control + [5:5] + + + SYSCTL_SRCR2_GPIOG + Port G Reset Control + [6:6] + + + SYSCTL_SRCR2_EMAC0 + MAC0 Reset Control + [28:28] + + + SYSCTL_SRCR2_EPHY0 + PHY0 Reset Control + [30:30] + + + + + RIS + Raw Interrupt Status + 0x00000050 + + + SYSCTL_RIS_BORRIS + Brown-Out Reset Raw Interrupt Status + [1:1] + + + SYSCTL_RIS_PLLLRIS + PLL Lock Raw Interrupt Status + [6:6] + + + + + IMC + Interrupt Mask Control + 0x00000054 + + + SYSCTL_IMC_BORIM + Brown-Out Reset Interrupt Mask + [1:1] + + + SYSCTL_IMC_PLLLIM + PLL Lock Interrupt Mask + [6:6] + + + + + MISC + Masked Interrupt Status and Clear + 0x00000058 + + + SYSCTL_MISC_BORMIS + BOR Masked Interrupt Status + [1:1] + + + SYSCTL_MISC_PLLLMIS + PLL Lock Masked Interrupt Status + [6:6] + + + + + RESC + Reset Cause + 0x0000005C + + + SYSCTL_RESC_EXT + External Reset + [0:0] + + + SYSCTL_RESC_POR + Power-On Reset + [1:1] + + + SYSCTL_RESC_BOR + Brown-Out Reset + [2:2] + + + SYSCTL_RESC_SW + Software Reset + [4:4] + + + + + RCC + Run-Mode Clock Configuration + 0x00000060 + + + SYSCTL_RCC_MOSCDIS + Main Oscillator Disable + [0:0] + + + SYSCTL_RCC_IOSCDIS + Internal Oscillator Disable + [1:1] + + + SYSCTL_RCC_OSCSRC + Oscillator Source + [5:4] + + + SYSCTL_RCC_OSCSRC_MAIN + MOSC + 0x0 + + + SYSCTL_RCC_OSCSRC_INT + IOSC + 0x1 + + + SYSCTL_RCC_OSCSRC_INT4 + IOSC/4 + 0x2 + + + SYSCTL_RCC_OSCSRC_30 + 30 kHz + 0x3 + + + + + SYSCTL_RCC_XTAL + Crystal Value + [9:6] + + + SYSCTL_RCC_XTAL_1MHZ + 1 MHz + 0x0 + + + SYSCTL_RCC_XTAL_1_84MHZ + 1.8432 MHz + 0x1 + + + SYSCTL_RCC_XTAL_2MHZ + 2 MHz + 0x2 + + + SYSCTL_RCC_XTAL_2_45MHZ + 2.4576 MHz + 0x3 + + + SYSCTL_RCC_XTAL_3_57MHZ + 3.579545 MHz + 0x4 + + + SYSCTL_RCC_XTAL_3_68MHZ + 3.6864 MHz + 0x5 + + + SYSCTL_RCC_XTAL_4MHZ + 4 MHz + 0x6 + + + SYSCTL_RCC_XTAL_4_09MHZ + 4.096 MHz + 0x7 + + + SYSCTL_RCC_XTAL_4_91MHZ + 4.9152 MHz + 0x8 + + + SYSCTL_RCC_XTAL_5MHZ + 5 MHz + 0x9 + + + SYSCTL_RCC_XTAL_5_12MHZ + 5.12 MHz + 0xa + + + SYSCTL_RCC_XTAL_6MHZ + 6 MHz + 0xb + + + SYSCTL_RCC_XTAL_6_14MHZ + 6.144 MHz + 0xc + + + SYSCTL_RCC_XTAL_7_37MHZ + 7.3728 MHz + 0xd + + + SYSCTL_RCC_XTAL_8MHZ + 8 MHz + 0xe + + + SYSCTL_RCC_XTAL_8_19MHZ + 8.192 MHz + 0xf + + + + + SYSCTL_RCC_BYPASS + PLL Bypass + [11:11] + + + SYSCTL_RCC_PWRDN + PLL Power Down + [13:13] + + + SYSCTL_RCC_PWMDIV + PWM Unit Clock Divisor + [19:17] + + + SYSCTL_RCC_PWMDIV_2 + PWM clock /2 + 0x0 + + + SYSCTL_RCC_PWMDIV_4 + PWM clock /4 + 0x1 + + + SYSCTL_RCC_PWMDIV_8 + PWM clock /8 + 0x2 + + + SYSCTL_RCC_PWMDIV_16 + PWM clock /16 + 0x3 + + + SYSCTL_RCC_PWMDIV_32 + PWM clock /32 + 0x4 + + + SYSCTL_RCC_PWMDIV_64 + PWM clock /64 + 0x5 + + + + + SYSCTL_RCC_USEPWMDIV + Enable PWM Clock Divisor + [20:20] + + + SYSCTL_RCC_USESYSDIV + Enable System Clock Divider + [22:22] + + + SYSCTL_RCC_SYSDIV + System Clock Divisor + [26:23] + + + SYSCTL_RCC_SYSDIV_2 + System clock /2 + 0x1 + + + SYSCTL_RCC_SYSDIV_3 + System clock /3 + 0x2 + + + SYSCTL_RCC_SYSDIV_4 + System clock /4 + 0x3 + + + SYSCTL_RCC_SYSDIV_5 + System clock /5 + 0x4 + + + SYSCTL_RCC_SYSDIV_6 + System clock /6 + 0x5 + + + SYSCTL_RCC_SYSDIV_7 + System clock /7 + 0x6 + + + SYSCTL_RCC_SYSDIV_8 + System clock /8 + 0x7 + + + SYSCTL_RCC_SYSDIV_9 + System clock /9 + 0x8 + + + SYSCTL_RCC_SYSDIV_10 + System clock /10 + 0x9 + + + SYSCTL_RCC_SYSDIV_11 + System clock /11 + 0xa + + + SYSCTL_RCC_SYSDIV_12 + System clock /12 + 0xb + + + SYSCTL_RCC_SYSDIV_13 + System clock /13 + 0xc + + + SYSCTL_RCC_SYSDIV_14 + System clock /14 + 0xd + + + SYSCTL_RCC_SYSDIV_15 + System clock /15 + 0xe + + + SYSCTL_RCC_SYSDIV_16 + System clock /16 + 0xf + + + + + SYSCTL_RCC_ACG + Auto Clock Gating + [27:27] + + + + + PLLCFG + XTAL to PLL Translation + 0x00000064 + + + SYSCTL_PLLCFG_R + PLL R Value + [4:0] + + + SYSCTL_PLLCFG_F + PLL F Value + [13:5] + + + + + RCC2 + Run-Mode Clock Configuration 2 + 0x00000070 + + + SYSCTL_RCC2_OSCSRC2 + Oscillator Source 2 + [6:4] + + + SYSCTL_RCC2_OSCSRC2_MO + MOSC + 0x0 + + + SYSCTL_RCC2_OSCSRC2_IO + PIOSC + 0x1 + + + SYSCTL_RCC2_OSCSRC2_IO4 + PIOSC/4 + 0x2 + + + SYSCTL_RCC2_OSCSRC2_30 + 30 kHz + 0x3 + + + SYSCTL_RCC2_OSCSRC2_32 + 32.768 kHz + 0x7 + + + + + SYSCTL_RCC2_BYPASS2 + PLL Bypass 2 + [11:11] + + + SYSCTL_RCC2_PWRDN2 + Power-Down PLL 2 + [13:13] + + + SYSCTL_RCC2_SYSDIV2 + System Clock Divisor 2 + [28:23] + + + SYSCTL_RCC2_SYSDIV2_2 + System clock /2 + 0x1 + + + SYSCTL_RCC2_SYSDIV2_3 + System clock /3 + 0x2 + + + SYSCTL_RCC2_SYSDIV2_4 + System clock /4 + 0x3 + + + SYSCTL_RCC2_SYSDIV2_5 + System clock /5 + 0x4 + + + SYSCTL_RCC2_SYSDIV2_6 + System clock /6 + 0x5 + + + SYSCTL_RCC2_SYSDIV2_7 + System clock /7 + 0x6 + + + SYSCTL_RCC2_SYSDIV2_8 + System clock /8 + 0x7 + + + SYSCTL_RCC2_SYSDIV2_9 + System clock /9 + 0x8 + + + SYSCTL_RCC2_SYSDIV2_10 + System clock /10 + 0x9 + + + SYSCTL_RCC2_SYSDIV2_11 + System clock /11 + 0xa + + + SYSCTL_RCC2_SYSDIV2_12 + System clock /12 + 0xb + + + SYSCTL_RCC2_SYSDIV2_13 + System clock /13 + 0xc + + + SYSCTL_RCC2_SYSDIV2_14 + System clock /14 + 0xd + + + SYSCTL_RCC2_SYSDIV2_15 + System clock /15 + 0xe + + + SYSCTL_RCC2_SYSDIV2_16 + System clock /16 + 0xf + + + SYSCTL_RCC2_SYSDIV2_17 + System clock /17 + 0x10 + + + SYSCTL_RCC2_SYSDIV2_18 + System clock /18 + 0x11 + + + SYSCTL_RCC2_SYSDIV2_19 + System clock /19 + 0x12 + + + SYSCTL_RCC2_SYSDIV2_20 + System clock /20 + 0x13 + + + SYSCTL_RCC2_SYSDIV2_21 + System clock /21 + 0x14 + + + SYSCTL_RCC2_SYSDIV2_22 + System clock /22 + 0x15 + + + SYSCTL_RCC2_SYSDIV2_23 + System clock /23 + 0x16 + + + SYSCTL_RCC2_SYSDIV2_24 + System clock /24 + 0x17 + + + SYSCTL_RCC2_SYSDIV2_25 + System clock /25 + 0x18 + + + SYSCTL_RCC2_SYSDIV2_26 + System clock /26 + 0x19 + + + SYSCTL_RCC2_SYSDIV2_27 + System clock /27 + 0x1a + + + SYSCTL_RCC2_SYSDIV2_28 + System clock /28 + 0x1b + + + SYSCTL_RCC2_SYSDIV2_29 + System clock /29 + 0x1c + + + SYSCTL_RCC2_SYSDIV2_30 + System clock /30 + 0x1d + + + SYSCTL_RCC2_SYSDIV2_31 + System clock /31 + 0x1e + + + SYSCTL_RCC2_SYSDIV2_32 + System clock /32 + 0x1f + + + SYSCTL_RCC2_SYSDIV2_33 + System clock /33 + 0x20 + + + SYSCTL_RCC2_SYSDIV2_34 + System clock /34 + 0x21 + + + SYSCTL_RCC2_SYSDIV2_35 + System clock /35 + 0x22 + + + SYSCTL_RCC2_SYSDIV2_36 + System clock /36 + 0x23 + + + SYSCTL_RCC2_SYSDIV2_37 + System clock /37 + 0x24 + + + SYSCTL_RCC2_SYSDIV2_38 + System clock /38 + 0x25 + + + SYSCTL_RCC2_SYSDIV2_39 + System clock /39 + 0x26 + + + SYSCTL_RCC2_SYSDIV2_40 + System clock /40 + 0x27 + + + SYSCTL_RCC2_SYSDIV2_41 + System clock /41 + 0x28 + + + SYSCTL_RCC2_SYSDIV2_42 + System clock /42 + 0x29 + + + SYSCTL_RCC2_SYSDIV2_43 + System clock /43 + 0x2a + + + SYSCTL_RCC2_SYSDIV2_44 + System clock /44 + 0x2b + + + SYSCTL_RCC2_SYSDIV2_45 + System clock /45 + 0x2c + + + SYSCTL_RCC2_SYSDIV2_46 + System clock /46 + 0x2d + + + SYSCTL_RCC2_SYSDIV2_47 + System clock /47 + 0x2e + + + SYSCTL_RCC2_SYSDIV2_48 + System clock /48 + 0x2f + + + SYSCTL_RCC2_SYSDIV2_49 + System clock /49 + 0x30 + + + SYSCTL_RCC2_SYSDIV2_50 + System clock /50 + 0x31 + + + SYSCTL_RCC2_SYSDIV2_51 + System clock /51 + 0x32 + + + SYSCTL_RCC2_SYSDIV2_52 + System clock /52 + 0x33 + + + SYSCTL_RCC2_SYSDIV2_53 + System clock /53 + 0x34 + + + SYSCTL_RCC2_SYSDIV2_54 + System clock /54 + 0x35 + + + SYSCTL_RCC2_SYSDIV2_55 + System clock /55 + 0x36 + + + SYSCTL_RCC2_SYSDIV2_56 + System clock /56 + 0x37 + + + SYSCTL_RCC2_SYSDIV2_57 + System clock /57 + 0x38 + + + SYSCTL_RCC2_SYSDIV2_58 + System clock /58 + 0x39 + + + SYSCTL_RCC2_SYSDIV2_59 + System clock /59 + 0x3a + + + SYSCTL_RCC2_SYSDIV2_60 + System clock /60 + 0x3b + + + SYSCTL_RCC2_SYSDIV2_61 + System clock /61 + 0x3c + + + SYSCTL_RCC2_SYSDIV2_62 + System clock /62 + 0x3d + + + SYSCTL_RCC2_SYSDIV2_63 + System clock /63 + 0x3e + + + SYSCTL_RCC2_SYSDIV2_64 + System clock /64 + 0x3f + + + + + SYSCTL_RCC2_USERCC2 + Use RCC2 + [31:31] + + + + + RCGC0 + Run Mode Clock Gating Control Register 0 + 0x00000100 + + + SYSCTL_RCGC0_HIB + HIB Clock Gating Control + [6:6] + + + SYSCTL_RCGC0_ADCSPD + ADC Sample Speed + [9:8] + + + SYSCTL_RCGC0_ADCSPD125K + 125K samples/second + 0x0 + + + SYSCTL_RCGC0_ADCSPD250K + 250K samples/second + 0x1 + + + SYSCTL_RCGC0_ADCSPD500K + 500K samples/second + 0x2 + + + SYSCTL_RCGC0_ADCSPD1M + 1M samples/second + 0x3 + + + + + + + RCGC1 + Run Mode Clock Gating Control Register 1 + 0x00000104 + + + SYSCTL_RCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_RCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_RCGC1_UART2 + UART2 Clock Gating Control + [2:2] + + + SYSCTL_RCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_RCGC1_QEI0 + QEI0 Clock Gating Control + [8:8] + + + SYSCTL_RCGC1_QEI1 + QEI1 Clock Gating Control + [9:9] + + + SYSCTL_RCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_RCGC1_I2C1 + I2C1 Clock Gating Control + [14:14] + + + SYSCTL_RCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_RCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_RCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_RCGC1_TIMER3 + Timer 3 Clock Gating Control + [19:19] + + + SYSCTL_RCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + SYSCTL_RCGC1_COMP1 + Analog Comparator 1 Clock Gating + [25:25] + + + + + RCGC2 + Run Mode Clock Gating Control Register 2 + 0x00000108 + + + SYSCTL_RCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_RCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_RCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_RCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_RCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + SYSCTL_RCGC2_GPIOF + Port F Clock Gating Control + [5:5] + + + SYSCTL_RCGC2_GPIOG + Port G Clock Gating Control + [6:6] + + + SYSCTL_RCGC2_EMAC0 + MAC0 Clock Gating Control + [28:28] + + + SYSCTL_RCGC2_EPHY0 + PHY0 Clock Gating Control + [30:30] + + + + + SCGC0 + Sleep Mode Clock Gating Control Register 0 + 0x00000110 + + + SYSCTL_SCGC0_HIB + HIB Clock Gating Control + [6:6] + + + SYSCTL_SCGC0_ADCSPD + ADC Sample Speed + [9:8] + + + SYSCTL_SCGC0_ADCSPD125K + 125K samples/second + 0x0 + + + SYSCTL_SCGC0_ADCSPD250K + 250K samples/second + 0x1 + + + SYSCTL_SCGC0_ADCSPD500K + 500K samples/second + 0x2 + + + SYSCTL_SCGC0_ADCSPD1M + 1M samples/second + 0x3 + + + + + + + SCGC1 + Sleep Mode Clock Gating Control Register 1 + 0x00000114 + + + SYSCTL_SCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_SCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_SCGC1_UART2 + UART2 Clock Gating Control + [2:2] + + + SYSCTL_SCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_SCGC1_QEI0 + QEI0 Clock Gating Control + [8:8] + + + SYSCTL_SCGC1_QEI1 + QEI1 Clock Gating Control + [9:9] + + + SYSCTL_SCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_SCGC1_I2C1 + I2C1 Clock Gating Control + [14:14] + + + SYSCTL_SCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_SCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_SCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_SCGC1_TIMER3 + Timer 3 Clock Gating Control + [19:19] + + + SYSCTL_SCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + SYSCTL_SCGC1_COMP1 + Analog Comparator 1 Clock Gating + [25:25] + + + + + SCGC2 + Sleep Mode Clock Gating Control Register 2 + 0x00000118 + + + SYSCTL_SCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_SCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_SCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_SCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_SCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + SYSCTL_SCGC2_GPIOF + Port F Clock Gating Control + [5:5] + + + SYSCTL_SCGC2_GPIOG + Port G Clock Gating Control + [6:6] + + + SYSCTL_SCGC2_EMAC0 + MAC0 Clock Gating Control + [28:28] + + + SYSCTL_SCGC2_EPHY0 + PHY0 Clock Gating Control + [30:30] + + + + + DCGC0 + Deep Sleep Mode Clock Gating Control Register 0 + 0x00000120 + + + SYSCTL_DCGC0_HIB + HIB Clock Gating Control + [6:6] + + + + + DCGC1 + Deep-Sleep Mode Clock Gating Control Register 1 + 0x00000124 + + + SYSCTL_DCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_DCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_DCGC1_UART2 + UART2 Clock Gating Control + [2:2] + + + SYSCTL_DCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_DCGC1_QEI0 + QEI0 Clock Gating Control + [8:8] + + + SYSCTL_DCGC1_QEI1 + QEI1 Clock Gating Control + [9:9] + + + SYSCTL_DCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_DCGC1_I2C1 + I2C1 Clock Gating Control + [14:14] + + + SYSCTL_DCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_DCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_DCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_DCGC1_TIMER3 + Timer 3 Clock Gating Control + [19:19] + + + SYSCTL_DCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + SYSCTL_DCGC1_COMP1 + Analog Comparator 1 Clock Gating + [25:25] + + + + + DCGC2 + Deep Sleep Mode Clock Gating Control Register 2 + 0x00000128 + + + SYSCTL_DCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_DCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_DCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_DCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_DCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + SYSCTL_DCGC2_GPIOF + Port F Clock Gating Control + [5:5] + + + SYSCTL_DCGC2_GPIOG + Port G Clock Gating Control + [6:6] + + + SYSCTL_DCGC2_EMAC0 + MAC0 Clock Gating Control + [28:28] + + + SYSCTL_DCGC2_EPHY0 + PHY0 Clock Gating Control + [30:30] + + + + + DSLPCLKCFG + Deep Sleep Clock Configuration + 0x00000144 + + + SYSCTL_DSLPCLKCFG_O + Clock Source + [6:4] + + + SYSCTL_DSLPCLKCFG_O_IGN + MOSC + 0x0 + + + SYSCTL_DSLPCLKCFG_O_IO + PIOSC + 0x1 + + + SYSCTL_DSLPCLKCFG_O_30 + 30 kHz + 0x3 + + + SYSCTL_DSLPCLKCFG_O_32 + 32.768 kHz + 0x7 + + + + + SYSCTL_DSLPCLKCFG_D + Divider Field Override + [28:23] + + + SYSCTL_DSLPCLKCFG_D_1 + System clock /1 + 0x0 + + + SYSCTL_DSLPCLKCFG_D_2 + System clock /2 + 0x1 + + + SYSCTL_DSLPCLKCFG_D_3 + System clock /3 + 0x2 + + + SYSCTL_DSLPCLKCFG_D_4 + System clock /4 + 0x3 + + + SYSCTL_DSLPCLKCFG_D_5 + System clock /5 + 0x4 + + + SYSCTL_DSLPCLKCFG_D_6 + System clock /6 + 0x5 + + + SYSCTL_DSLPCLKCFG_D_7 + System clock /7 + 0x6 + + + SYSCTL_DSLPCLKCFG_D_8 + System clock /8 + 0x7 + + + SYSCTL_DSLPCLKCFG_D_9 + System clock /9 + 0x8 + + + SYSCTL_DSLPCLKCFG_D_10 + System clock /10 + 0x9 + + + SYSCTL_DSLPCLKCFG_D_11 + System clock /11 + 0xa + + + SYSCTL_DSLPCLKCFG_D_12 + System clock /12 + 0xb + + + SYSCTL_DSLPCLKCFG_D_13 + System clock /13 + 0xc + + + SYSCTL_DSLPCLKCFG_D_14 + System clock /14 + 0xd + + + SYSCTL_DSLPCLKCFG_D_15 + System clock /15 + 0xe + + + SYSCTL_DSLPCLKCFG_D_16 + System clock /16 + 0xf + + + SYSCTL_DSLPCLKCFG_D_17 + System clock /17 + 0x10 + + + SYSCTL_DSLPCLKCFG_D_18 + System clock /18 + 0x11 + + + SYSCTL_DSLPCLKCFG_D_19 + System clock /19 + 0x12 + + + SYSCTL_DSLPCLKCFG_D_20 + System clock /20 + 0x13 + + + SYSCTL_DSLPCLKCFG_D_21 + System clock /21 + 0x14 + + + SYSCTL_DSLPCLKCFG_D_22 + System clock /22 + 0x15 + + + SYSCTL_DSLPCLKCFG_D_23 + System clock /23 + 0x16 + + + SYSCTL_DSLPCLKCFG_D_24 + System clock /24 + 0x17 + + + SYSCTL_DSLPCLKCFG_D_25 + System clock /25 + 0x18 + + + SYSCTL_DSLPCLKCFG_D_26 + System clock /26 + 0x19 + + + SYSCTL_DSLPCLKCFG_D_27 + System clock /27 + 0x1a + + + SYSCTL_DSLPCLKCFG_D_28 + System clock /28 + 0x1b + + + SYSCTL_DSLPCLKCFG_D_29 + System clock /29 + 0x1c + + + SYSCTL_DSLPCLKCFG_D_30 + System clock /30 + 0x1d + + + SYSCTL_DSLPCLKCFG_D_31 + System clock /31 + 0x1e + + + SYSCTL_DSLPCLKCFG_D_32 + System clock /32 + 0x1f + + + SYSCTL_DSLPCLKCFG_D_33 + System clock /33 + 0x20 + + + SYSCTL_DSLPCLKCFG_D_34 + System clock /34 + 0x21 + + + SYSCTL_DSLPCLKCFG_D_35 + System clock /35 + 0x22 + + + SYSCTL_DSLPCLKCFG_D_36 + System clock /36 + 0x23 + + + SYSCTL_DSLPCLKCFG_D_37 + System clock /37 + 0x24 + + + SYSCTL_DSLPCLKCFG_D_38 + System clock /38 + 0x25 + + + SYSCTL_DSLPCLKCFG_D_39 + System clock /39 + 0x26 + + + SYSCTL_DSLPCLKCFG_D_40 + System clock /40 + 0x27 + + + SYSCTL_DSLPCLKCFG_D_41 + System clock /41 + 0x28 + + + SYSCTL_DSLPCLKCFG_D_42 + System clock /42 + 0x29 + + + SYSCTL_DSLPCLKCFG_D_43 + System clock /43 + 0x2a + + + SYSCTL_DSLPCLKCFG_D_44 + System clock /44 + 0x2b + + + SYSCTL_DSLPCLKCFG_D_45 + System clock /45 + 0x2c + + + SYSCTL_DSLPCLKCFG_D_46 + System clock /46 + 0x2d + + + SYSCTL_DSLPCLKCFG_D_47 + System clock /47 + 0x2e + + + SYSCTL_DSLPCLKCFG_D_48 + System clock /48 + 0x2f + + + SYSCTL_DSLPCLKCFG_D_49 + System clock /49 + 0x30 + + + SYSCTL_DSLPCLKCFG_D_50 + System clock /50 + 0x31 + + + SYSCTL_DSLPCLKCFG_D_51 + System clock /51 + 0x32 + + + SYSCTL_DSLPCLKCFG_D_52 + System clock /52 + 0x33 + + + SYSCTL_DSLPCLKCFG_D_53 + System clock /53 + 0x34 + + + SYSCTL_DSLPCLKCFG_D_54 + System clock /54 + 0x35 + + + SYSCTL_DSLPCLKCFG_D_55 + System clock /55 + 0x36 + + + SYSCTL_DSLPCLKCFG_D_56 + System clock /56 + 0x37 + + + SYSCTL_DSLPCLKCFG_D_57 + System clock /57 + 0x38 + + + SYSCTL_DSLPCLKCFG_D_58 + System clock /58 + 0x39 + + + SYSCTL_DSLPCLKCFG_D_59 + System clock /59 + 0x3a + + + SYSCTL_DSLPCLKCFG_D_60 + System clock /60 + 0x3b + + + SYSCTL_DSLPCLKCFG_D_61 + System clock /61 + 0x3c + + + SYSCTL_DSLPCLKCFG_D_62 + System clock /62 + 0x3d + + + SYSCTL_DSLPCLKCFG_D_63 + System clock /63 + 0x3e + + + SYSCTL_DSLPCLKCFG_D_64 + System clock /64 + 0x3f + + + + + + + + + NVIC + Register map for NVIC peripheral + NVIC + NVIC + 0xE000E000 + + 0 + 0x00001000 + registers + + + + INT_TYPE + Interrupt Controller Type Reg + 0x00000004 + + + NVIC_INT_TYPE_LINES + Number of interrupt lines (x32) + [4:0] + + + + + ST_CTRL + SysTick Control and Status Register + 0x00000010 + + + NVIC_ST_CTRL_ENABLE + Enable + [0:0] + + + NVIC_ST_CTRL_INTEN + Interrupt Enable + [1:1] + + + NVIC_ST_CTRL_CLK_SRC + Clock Source + [2:2] + + + NVIC_ST_CTRL_COUNT + Count Flag + [16:16] + + + + + ST_RELOAD + SysTick Reload Value Register + 0x00000014 + + + NVIC_ST_RELOAD + Reload Value + [23:0] + + + + + ST_CURRENT + SysTick Current Value Register + 0x00000018 + + + NVIC_ST_CURRENT + Current Value + [23:0] + + + + + ST_CAL + SysTick Calibration Value Reg + 0x0000001C + + + NVIC_ST_CAL_ONEMS + 1ms reference value + [23:0] + + + NVIC_ST_CAL_SKEW + Clock skew + [30:30] + + + NVIC_ST_CAL_NOREF + No reference clock + [31:31] + + + + + EN0 + Interrupt 0-31 Set Enable + 0x00000100 + + + NVIC_EN0_INT + Interrupt Enable + [31:0] + + + NVIC_EN0_INT0 + Interrupt 0 enable + 0x1 + + + NVIC_EN0_INT1 + Interrupt 1 enable + 0x2 + + + NVIC_EN0_INT2 + Interrupt 2 enable + 0x4 + + + NVIC_EN0_INT3 + Interrupt 3 enable + 0x8 + + + NVIC_EN0_INT4 + Interrupt 4 enable + 0x10 + + + NVIC_EN0_INT5 + Interrupt 5 enable + 0x20 + + + NVIC_EN0_INT6 + Interrupt 6 enable + 0x40 + + + NVIC_EN0_INT7 + Interrupt 7 enable + 0x80 + + + NVIC_EN0_INT8 + Interrupt 8 enable + 0x100 + + + NVIC_EN0_INT9 + Interrupt 9 enable + 0x200 + + + NVIC_EN0_INT10 + Interrupt 10 enable + 0x400 + + + NVIC_EN0_INT11 + Interrupt 11 enable + 0x800 + + + NVIC_EN0_INT12 + Interrupt 12 enable + 0x1000 + + + NVIC_EN0_INT13 + Interrupt 13 enable + 0x2000 + + + NVIC_EN0_INT14 + Interrupt 14 enable + 0x4000 + + + NVIC_EN0_INT15 + Interrupt 15 enable + 0x8000 + + + NVIC_EN0_INT16 + Interrupt 16 enable + 0x10000 + + + NVIC_EN0_INT17 + Interrupt 17 enable + 0x20000 + + + NVIC_EN0_INT18 + Interrupt 18 enable + 0x40000 + + + NVIC_EN0_INT19 + Interrupt 19 enable + 0x80000 + + + NVIC_EN0_INT20 + Interrupt 20 enable + 0x100000 + + + NVIC_EN0_INT21 + Interrupt 21 enable + 0x200000 + + + NVIC_EN0_INT22 + Interrupt 22 enable + 0x400000 + + + NVIC_EN0_INT23 + Interrupt 23 enable + 0x800000 + + + NVIC_EN0_INT24 + Interrupt 24 enable + 0x1000000 + + + NVIC_EN0_INT25 + Interrupt 25 enable + 0x2000000 + + + NVIC_EN0_INT26 + Interrupt 26 enable + 0x4000000 + + + NVIC_EN0_INT27 + Interrupt 27 enable + 0x8000000 + + + NVIC_EN0_INT28 + Interrupt 28 enable + 0x10000000 + + + NVIC_EN0_INT29 + Interrupt 29 enable + 0x20000000 + + + NVIC_EN0_INT30 + Interrupt 30 enable + 0x40000000 + + + NVIC_EN0_INT31 + Interrupt 31 enable + 0x80000000 + + + + + + + EN1 + Interrupt 32-54 Set Enable + 0x00000104 + + + NVIC_EN1_INT + Interrupt Enable + [11:0] + + + NVIC_EN1_INT32 + Interrupt 32 enable + 0x1 + + + NVIC_EN1_INT33 + Interrupt 33 enable + 0x2 + + + NVIC_EN1_INT34 + Interrupt 34 enable + 0x4 + + + NVIC_EN1_INT35 + Interrupt 35 enable + 0x8 + + + NVIC_EN1_INT36 + Interrupt 36 enable + 0x10 + + + NVIC_EN1_INT37 + Interrupt 37 enable + 0x20 + + + NVIC_EN1_INT38 + Interrupt 38 enable + 0x40 + + + NVIC_EN1_INT39 + Interrupt 39 enable + 0x80 + + + NVIC_EN1_INT40 + Interrupt 40 enable + 0x100 + + + NVIC_EN1_INT41 + Interrupt 41 enable + 0x200 + + + NVIC_EN1_INT42 + Interrupt 42 enable + 0x400 + + + NVIC_EN1_INT43 + Interrupt 43 enable + 0x800 + + + + + + + DIS0 + Interrupt 0-31 Clear Enable + 0x00000180 + + + NVIC_DIS0_INT + Interrupt Disable + [31:0] + + + NVIC_DIS0_INT0 + Interrupt 0 disable + 0x1 + + + NVIC_DIS0_INT1 + Interrupt 1 disable + 0x2 + + + NVIC_DIS0_INT2 + Interrupt 2 disable + 0x4 + + + NVIC_DIS0_INT3 + Interrupt 3 disable + 0x8 + + + NVIC_DIS0_INT4 + Interrupt 4 disable + 0x10 + + + NVIC_DIS0_INT5 + Interrupt 5 disable + 0x20 + + + NVIC_DIS0_INT6 + Interrupt 6 disable + 0x40 + + + NVIC_DIS0_INT7 + Interrupt 7 disable + 0x80 + + + NVIC_DIS0_INT8 + Interrupt 8 disable + 0x100 + + + NVIC_DIS0_INT9 + Interrupt 9 disable + 0x200 + + + NVIC_DIS0_INT10 + Interrupt 10 disable + 0x400 + + + NVIC_DIS0_INT11 + Interrupt 11 disable + 0x800 + + + NVIC_DIS0_INT12 + Interrupt 12 disable + 0x1000 + + + NVIC_DIS0_INT13 + Interrupt 13 disable + 0x2000 + + + NVIC_DIS0_INT14 + Interrupt 14 disable + 0x4000 + + + NVIC_DIS0_INT15 + Interrupt 15 disable + 0x8000 + + + NVIC_DIS0_INT16 + Interrupt 16 disable + 0x10000 + + + NVIC_DIS0_INT17 + Interrupt 17 disable + 0x20000 + + + NVIC_DIS0_INT18 + Interrupt 18 disable + 0x40000 + + + NVIC_DIS0_INT19 + Interrupt 19 disable + 0x80000 + + + NVIC_DIS0_INT20 + Interrupt 20 disable + 0x100000 + + + NVIC_DIS0_INT21 + Interrupt 21 disable + 0x200000 + + + NVIC_DIS0_INT22 + Interrupt 22 disable + 0x400000 + + + NVIC_DIS0_INT23 + Interrupt 23 disable + 0x800000 + + + NVIC_DIS0_INT24 + Interrupt 24 disable + 0x1000000 + + + NVIC_DIS0_INT25 + Interrupt 25 disable + 0x2000000 + + + NVIC_DIS0_INT26 + Interrupt 26 disable + 0x4000000 + + + NVIC_DIS0_INT27 + Interrupt 27 disable + 0x8000000 + + + NVIC_DIS0_INT28 + Interrupt 28 disable + 0x10000000 + + + NVIC_DIS0_INT29 + Interrupt 29 disable + 0x20000000 + + + NVIC_DIS0_INT30 + Interrupt 30 disable + 0x40000000 + + + NVIC_DIS0_INT31 + Interrupt 31 disable + 0x80000000 + + + + + + + DIS1 + Interrupt 32-54 Clear Enable + 0x00000184 + + + NVIC_DIS1_INT + Interrupt Disable + [11:0] + + + NVIC_DIS1_INT32 + Interrupt 32 disable + 0x1 + + + NVIC_DIS1_INT33 + Interrupt 33 disable + 0x2 + + + NVIC_DIS1_INT34 + Interrupt 34 disable + 0x4 + + + NVIC_DIS1_INT35 + Interrupt 35 disable + 0x8 + + + NVIC_DIS1_INT36 + Interrupt 36 disable + 0x10 + + + NVIC_DIS1_INT37 + Interrupt 37 disable + 0x20 + + + NVIC_DIS1_INT38 + Interrupt 38 disable + 0x40 + + + NVIC_DIS1_INT39 + Interrupt 39 disable + 0x80 + + + NVIC_DIS1_INT40 + Interrupt 40 disable + 0x100 + + + NVIC_DIS1_INT41 + Interrupt 41 disable + 0x200 + + + NVIC_DIS1_INT42 + Interrupt 42 disable + 0x400 + + + NVIC_DIS1_INT43 + Interrupt 43 disable + 0x800 + + + + + + + PEND0 + Interrupt 0-31 Set Pending + 0x00000200 + + + NVIC_PEND0_INT + Interrupt Set Pending + [31:0] + + + NVIC_PEND0_INT0 + Interrupt 0 pend + 0x1 + + + NVIC_PEND0_INT1 + Interrupt 1 pend + 0x2 + + + NVIC_PEND0_INT2 + Interrupt 2 pend + 0x4 + + + NVIC_PEND0_INT3 + Interrupt 3 pend + 0x8 + + + NVIC_PEND0_INT4 + Interrupt 4 pend + 0x10 + + + NVIC_PEND0_INT5 + Interrupt 5 pend + 0x20 + + + NVIC_PEND0_INT6 + Interrupt 6 pend + 0x40 + + + NVIC_PEND0_INT7 + Interrupt 7 pend + 0x80 + + + NVIC_PEND0_INT8 + Interrupt 8 pend + 0x100 + + + NVIC_PEND0_INT9 + Interrupt 9 pend + 0x200 + + + NVIC_PEND0_INT10 + Interrupt 10 pend + 0x400 + + + NVIC_PEND0_INT11 + Interrupt 11 pend + 0x800 + + + NVIC_PEND0_INT12 + Interrupt 12 pend + 0x1000 + + + NVIC_PEND0_INT13 + Interrupt 13 pend + 0x2000 + + + NVIC_PEND0_INT14 + Interrupt 14 pend + 0x4000 + + + NVIC_PEND0_INT15 + Interrupt 15 pend + 0x8000 + + + NVIC_PEND0_INT16 + Interrupt 16 pend + 0x10000 + + + NVIC_PEND0_INT17 + Interrupt 17 pend + 0x20000 + + + NVIC_PEND0_INT18 + Interrupt 18 pend + 0x40000 + + + NVIC_PEND0_INT19 + Interrupt 19 pend + 0x80000 + + + NVIC_PEND0_INT20 + Interrupt 20 pend + 0x100000 + + + NVIC_PEND0_INT21 + Interrupt 21 pend + 0x200000 + + + NVIC_PEND0_INT22 + Interrupt 22 pend + 0x400000 + + + NVIC_PEND0_INT23 + Interrupt 23 pend + 0x800000 + + + NVIC_PEND0_INT24 + Interrupt 24 pend + 0x1000000 + + + NVIC_PEND0_INT25 + Interrupt 25 pend + 0x2000000 + + + NVIC_PEND0_INT26 + Interrupt 26 pend + 0x4000000 + + + NVIC_PEND0_INT27 + Interrupt 27 pend + 0x8000000 + + + NVIC_PEND0_INT28 + Interrupt 28 pend + 0x10000000 + + + NVIC_PEND0_INT29 + Interrupt 29 pend + 0x20000000 + + + NVIC_PEND0_INT30 + Interrupt 30 pend + 0x40000000 + + + NVIC_PEND0_INT31 + Interrupt 31 pend + 0x80000000 + + + + + + + PEND1 + Interrupt 32-54 Set Pending + 0x00000204 + + + NVIC_PEND1_INT + Interrupt Set Pending + [11:0] + + + NVIC_PEND1_INT32 + Interrupt 32 pend + 0x1 + + + NVIC_PEND1_INT33 + Interrupt 33 pend + 0x2 + + + NVIC_PEND1_INT34 + Interrupt 34 pend + 0x4 + + + NVIC_PEND1_INT35 + Interrupt 35 pend + 0x8 + + + NVIC_PEND1_INT36 + Interrupt 36 pend + 0x10 + + + NVIC_PEND1_INT37 + Interrupt 37 pend + 0x20 + + + NVIC_PEND1_INT38 + Interrupt 38 pend + 0x40 + + + NVIC_PEND1_INT39 + Interrupt 39 pend + 0x80 + + + NVIC_PEND1_INT40 + Interrupt 40 pend + 0x100 + + + NVIC_PEND1_INT41 + Interrupt 41 pend + 0x200 + + + NVIC_PEND1_INT42 + Interrupt 42 pend + 0x400 + + + NVIC_PEND1_INT43 + Interrupt 43 pend + 0x800 + + + + + + + UNPEND0 + Interrupt 0-31 Clear Pending + 0x00000280 + + + NVIC_UNPEND0_INT + Interrupt Clear Pending + [31:0] + + + NVIC_UNPEND0_INT0 + Interrupt 0 unpend + 0x1 + + + NVIC_UNPEND0_INT1 + Interrupt 1 unpend + 0x2 + + + NVIC_UNPEND0_INT2 + Interrupt 2 unpend + 0x4 + + + NVIC_UNPEND0_INT3 + Interrupt 3 unpend + 0x8 + + + NVIC_UNPEND0_INT4 + Interrupt 4 unpend + 0x10 + + + NVIC_UNPEND0_INT5 + Interrupt 5 unpend + 0x20 + + + NVIC_UNPEND0_INT6 + Interrupt 6 unpend + 0x40 + + + NVIC_UNPEND0_INT7 + Interrupt 7 unpend + 0x80 + + + NVIC_UNPEND0_INT8 + Interrupt 8 unpend + 0x100 + + + NVIC_UNPEND0_INT9 + Interrupt 9 unpend + 0x200 + + + NVIC_UNPEND0_INT10 + Interrupt 10 unpend + 0x400 + + + NVIC_UNPEND0_INT11 + Interrupt 11 unpend + 0x800 + + + NVIC_UNPEND0_INT12 + Interrupt 12 unpend + 0x1000 + + + NVIC_UNPEND0_INT13 + Interrupt 13 unpend + 0x2000 + + + NVIC_UNPEND0_INT14 + Interrupt 14 unpend + 0x4000 + + + NVIC_UNPEND0_INT15 + Interrupt 15 unpend + 0x8000 + + + NVIC_UNPEND0_INT16 + Interrupt 16 unpend + 0x10000 + + + NVIC_UNPEND0_INT17 + Interrupt 17 unpend + 0x20000 + + + NVIC_UNPEND0_INT18 + Interrupt 18 unpend + 0x40000 + + + NVIC_UNPEND0_INT19 + Interrupt 19 unpend + 0x80000 + + + NVIC_UNPEND0_INT20 + Interrupt 20 unpend + 0x100000 + + + NVIC_UNPEND0_INT21 + Interrupt 21 unpend + 0x200000 + + + NVIC_UNPEND0_INT22 + Interrupt 22 unpend + 0x400000 + + + NVIC_UNPEND0_INT23 + Interrupt 23 unpend + 0x800000 + + + NVIC_UNPEND0_INT24 + Interrupt 24 unpend + 0x1000000 + + + NVIC_UNPEND0_INT25 + Interrupt 25 unpend + 0x2000000 + + + NVIC_UNPEND0_INT26 + Interrupt 26 unpend + 0x4000000 + + + NVIC_UNPEND0_INT27 + Interrupt 27 unpend + 0x8000000 + + + NVIC_UNPEND0_INT28 + Interrupt 28 unpend + 0x10000000 + + + NVIC_UNPEND0_INT29 + Interrupt 29 unpend + 0x20000000 + + + NVIC_UNPEND0_INT30 + Interrupt 30 unpend + 0x40000000 + + + NVIC_UNPEND0_INT31 + Interrupt 31 unpend + 0x80000000 + + + + + + + UNPEND1 + Interrupt 32-54 Clear Pending + 0x00000284 + + + NVIC_UNPEND1_INT + Interrupt Clear Pending + [11:0] + + + NVIC_UNPEND1_INT32 + Interrupt 32 unpend + 0x1 + + + NVIC_UNPEND1_INT33 + Interrupt 33 unpend + 0x2 + + + NVIC_UNPEND1_INT34 + Interrupt 34 unpend + 0x4 + + + NVIC_UNPEND1_INT35 + Interrupt 35 unpend + 0x8 + + + NVIC_UNPEND1_INT36 + Interrupt 36 unpend + 0x10 + + + NVIC_UNPEND1_INT37 + Interrupt 37 unpend + 0x20 + + + NVIC_UNPEND1_INT38 + Interrupt 38 unpend + 0x40 + + + NVIC_UNPEND1_INT39 + Interrupt 39 unpend + 0x80 + + + NVIC_UNPEND1_INT40 + Interrupt 40 unpend + 0x100 + + + NVIC_UNPEND1_INT41 + Interrupt 41 unpend + 0x200 + + + NVIC_UNPEND1_INT42 + Interrupt 42 unpend + 0x400 + + + NVIC_UNPEND1_INT43 + Interrupt 43 unpend + 0x800 + + + + + + + ACTIVE0 + Interrupt 0-31 Active Bit + 0x00000300 + + + NVIC_ACTIVE0_INT + Interrupt Active + [31:0] + + + NVIC_ACTIVE0_INT0 + Interrupt 0 active + 0x1 + + + NVIC_ACTIVE0_INT1 + Interrupt 1 active + 0x2 + + + NVIC_ACTIVE0_INT2 + Interrupt 2 active + 0x4 + + + NVIC_ACTIVE0_INT3 + Interrupt 3 active + 0x8 + + + NVIC_ACTIVE0_INT4 + Interrupt 4 active + 0x10 + + + NVIC_ACTIVE0_INT5 + Interrupt 5 active + 0x20 + + + NVIC_ACTIVE0_INT6 + Interrupt 6 active + 0x40 + + + NVIC_ACTIVE0_INT7 + Interrupt 7 active + 0x80 + + + NVIC_ACTIVE0_INT8 + Interrupt 8 active + 0x100 + + + NVIC_ACTIVE0_INT9 + Interrupt 9 active + 0x200 + + + NVIC_ACTIVE0_INT10 + Interrupt 10 active + 0x400 + + + NVIC_ACTIVE0_INT11 + Interrupt 11 active + 0x800 + + + NVIC_ACTIVE0_INT12 + Interrupt 12 active + 0x1000 + + + NVIC_ACTIVE0_INT13 + Interrupt 13 active + 0x2000 + + + NVIC_ACTIVE0_INT14 + Interrupt 14 active + 0x4000 + + + NVIC_ACTIVE0_INT15 + Interrupt 15 active + 0x8000 + + + NVIC_ACTIVE0_INT16 + Interrupt 16 active + 0x10000 + + + NVIC_ACTIVE0_INT17 + Interrupt 17 active + 0x20000 + + + NVIC_ACTIVE0_INT18 + Interrupt 18 active + 0x40000 + + + NVIC_ACTIVE0_INT19 + Interrupt 19 active + 0x80000 + + + NVIC_ACTIVE0_INT20 + Interrupt 20 active + 0x100000 + + + NVIC_ACTIVE0_INT21 + Interrupt 21 active + 0x200000 + + + NVIC_ACTIVE0_INT22 + Interrupt 22 active + 0x400000 + + + NVIC_ACTIVE0_INT23 + Interrupt 23 active + 0x800000 + + + NVIC_ACTIVE0_INT24 + Interrupt 24 active + 0x1000000 + + + NVIC_ACTIVE0_INT25 + Interrupt 25 active + 0x2000000 + + + NVIC_ACTIVE0_INT26 + Interrupt 26 active + 0x4000000 + + + NVIC_ACTIVE0_INT27 + Interrupt 27 active + 0x8000000 + + + NVIC_ACTIVE0_INT28 + Interrupt 28 active + 0x10000000 + + + NVIC_ACTIVE0_INT29 + Interrupt 29 active + 0x20000000 + + + NVIC_ACTIVE0_INT30 + Interrupt 30 active + 0x40000000 + + + NVIC_ACTIVE0_INT31 + Interrupt 31 active + 0x80000000 + + + + + + + ACTIVE1 + Interrupt 32-54 Active Bit + 0x00000304 + + + NVIC_ACTIVE1_INT + Interrupt Active + [11:0] + + + NVIC_ACTIVE1_INT32 + Interrupt 32 active + 0x1 + + + NVIC_ACTIVE1_INT33 + Interrupt 33 active + 0x2 + + + NVIC_ACTIVE1_INT34 + Interrupt 34 active + 0x4 + + + NVIC_ACTIVE1_INT35 + Interrupt 35 active + 0x8 + + + NVIC_ACTIVE1_INT36 + Interrupt 36 active + 0x10 + + + NVIC_ACTIVE1_INT37 + Interrupt 37 active + 0x20 + + + NVIC_ACTIVE1_INT38 + Interrupt 38 active + 0x40 + + + NVIC_ACTIVE1_INT39 + Interrupt 39 active + 0x80 + + + NVIC_ACTIVE1_INT40 + Interrupt 40 active + 0x100 + + + NVIC_ACTIVE1_INT41 + Interrupt 41 active + 0x200 + + + NVIC_ACTIVE1_INT42 + Interrupt 42 active + 0x400 + + + NVIC_ACTIVE1_INT43 + Interrupt 43 active + 0x800 + + + + + + + PRI0 + Interrupt 0-3 Priority + 0x00000400 + + + NVIC_PRI0_INT0 + Interrupt 0 Priority Mask + [7:5] + + + NVIC_PRI0_INT1 + Interrupt 1 Priority Mask + [15:13] + + + NVIC_PRI0_INT2 + Interrupt 2 Priority Mask + [23:21] + + + NVIC_PRI0_INT3 + Interrupt 3 Priority Mask + [31:29] + + + + + PRI1 + Interrupt 4-7 Priority + 0x00000404 + + + NVIC_PRI1_INT4 + Interrupt 4 Priority Mask + [7:5] + + + NVIC_PRI1_INT5 + Interrupt 5 Priority Mask + [15:13] + + + NVIC_PRI1_INT6 + Interrupt 6 Priority Mask + [23:21] + + + NVIC_PRI1_INT7 + Interrupt 7 Priority Mask + [31:29] + + + + + PRI2 + Interrupt 8-11 Priority + 0x00000408 + + + NVIC_PRI2_INT8 + Interrupt 8 Priority Mask + [7:5] + + + NVIC_PRI2_INT9 + Interrupt 9 Priority Mask + [15:13] + + + NVIC_PRI2_INT10 + Interrupt 10 Priority Mask + [23:21] + + + NVIC_PRI2_INT11 + Interrupt 11 Priority Mask + [31:29] + + + + + PRI3 + Interrupt 12-15 Priority + 0x0000040C + + + NVIC_PRI3_INT12 + Interrupt 12 Priority Mask + [7:5] + + + NVIC_PRI3_INT13 + Interrupt 13 Priority Mask + [15:13] + + + NVIC_PRI3_INT14 + Interrupt 14 Priority Mask + [23:21] + + + NVIC_PRI3_INT15 + Interrupt 15 Priority Mask + [31:29] + + + + + PRI4 + Interrupt 16-19 Priority + 0x00000410 + + + NVIC_PRI4_INT16 + Interrupt 16 Priority Mask + [7:5] + + + NVIC_PRI4_INT17 + Interrupt 17 Priority Mask + [15:13] + + + NVIC_PRI4_INT18 + Interrupt 18 Priority Mask + [23:21] + + + NVIC_PRI4_INT19 + Interrupt 19 Priority Mask + [31:29] + + + + + PRI5 + Interrupt 20-23 Priority + 0x00000414 + + + NVIC_PRI5_INT20 + Interrupt 20 Priority Mask + [7:5] + + + NVIC_PRI5_INT21 + Interrupt 21 Priority Mask + [15:13] + + + NVIC_PRI5_INT22 + Interrupt 22 Priority Mask + [23:21] + + + NVIC_PRI5_INT23 + Interrupt 23 Priority Mask + [31:29] + + + + + PRI6 + Interrupt 24-27 Priority + 0x00000418 + + + NVIC_PRI6_INT24 + Interrupt 24 Priority Mask + [7:5] + + + NVIC_PRI6_INT25 + Interrupt 25 Priority Mask + [15:13] + + + NVIC_PRI6_INT26 + Interrupt 26 Priority Mask + [23:21] + + + NVIC_PRI6_INT27 + Interrupt 27 Priority Mask + [31:29] + + + + + PRI7 + Interrupt 28-31 Priority + 0x0000041C + + + NVIC_PRI7_INT28 + Interrupt 28 Priority Mask + [7:5] + + + NVIC_PRI7_INT29 + Interrupt 29 Priority Mask + [15:13] + + + NVIC_PRI7_INT30 + Interrupt 30 Priority Mask + [23:21] + + + NVIC_PRI7_INT31 + Interrupt 31 Priority Mask + [31:29] + + + + + PRI8 + Interrupt 32-35 Priority + 0x00000420 + + + NVIC_PRI8_INT32 + Interrupt 32 Priority Mask + [7:5] + + + NVIC_PRI8_INT33 + Interrupt 33 Priority Mask + [15:13] + + + NVIC_PRI8_INT34 + Interrupt 34 Priority Mask + [23:21] + + + NVIC_PRI8_INT35 + Interrupt 35 Priority Mask + [31:29] + + + + + PRI9 + Interrupt 36-39 Priority + 0x00000424 + + + NVIC_PRI9_INT36 + Interrupt 36 Priority Mask + [7:5] + + + NVIC_PRI9_INT37 + Interrupt 37 Priority Mask + [15:13] + + + NVIC_PRI9_INT38 + Interrupt 38 Priority Mask + [23:21] + + + NVIC_PRI9_INT39 + Interrupt 39 Priority Mask + [31:29] + + + + + PRI10 + Interrupt 40-43 Priority + 0x00000428 + + + NVIC_PRI10_INT40 + Interrupt 40 Priority Mask + [7:5] + + + NVIC_PRI10_INT41 + Interrupt 41 Priority Mask + [15:13] + + + NVIC_PRI10_INT42 + Interrupt 42 Priority Mask + [23:21] + + + NVIC_PRI10_INT43 + Interrupt 43 Priority Mask + [31:29] + + + + + CPUID + CPU ID Base + 0x00000D00 + + + NVIC_CPUID_REV + Revision Number + [3:0] + + + NVIC_CPUID_PARTNO + Part Number + [15:4] + + + NVIC_CPUID_PARTNO_CM3 + Cortex-M3 processor + 0xc23 + + + + + NVIC_CPUID_CON + Constant + [19:16] + + + NVIC_CPUID_VAR + Variant Number + [23:20] + + + NVIC_CPUID_IMP + Implementer Code + [31:24] + + + NVIC_CPUID_IMP_ARM + ARM + 0x41 + + + + + + + INT_CTRL + Interrupt Control and State + 0x00000D04 + + + NVIC_INT_CTRL_VEC_ACT + Interrupt Pending Vector Number + [5:0] + + + NVIC_INT_CTRL_RET_BASE + Return to Base + [11:11] + + + NVIC_INT_CTRL_VEC_PEN + Interrupt Pending Vector Number + [17:12] + + + NVIC_INT_CTRL_VEC_PEN_NMI + NMI + 0x2 + + + NVIC_INT_CTRL_VEC_PEN_HARD + Hard fault + 0x3 + + + NVIC_INT_CTRL_VEC_PEN_MEM + Memory management fault + 0x4 + + + NVIC_INT_CTRL_VEC_PEN_BUS + Bus fault + 0x5 + + + NVIC_INT_CTRL_VEC_PEN_USG + Usage fault + 0x6 + + + NVIC_INT_CTRL_VEC_PEN_SVC + SVCall + 0xb + + + NVIC_INT_CTRL_VEC_PEN_PNDSV + PendSV + 0xe + + + NVIC_INT_CTRL_VEC_PEN_TICK + SysTick + 0xf + + + + + NVIC_INT_CTRL_ISR_PEND + Interrupt Pending + [22:22] + + + NVIC_INT_CTRL_ISR_PRE + Debug Interrupt Handling + [23:23] + + + NVIC_INT_CTRL_PENDSTCLR + SysTick Clear Pending + [25:25] + + + NVIC_INT_CTRL_PENDSTSET + SysTick Set Pending + [26:26] + + + NVIC_INT_CTRL_UNPEND_SV + PendSV Clear Pending + [27:27] + + + NVIC_INT_CTRL_PEND_SV + PendSV Set Pending + [28:28] + + + NVIC_INT_CTRL_NMI_SET + NMI Set Pending + [31:31] + + + + + VTABLE + Vector Table Offset + 0x00000D08 + + + NVIC_VTABLE_OFFSET + Vector Table Offset + [28:8] + + + NVIC_VTABLE_BASE + Vector Table Base + [29:29] + + + + + APINT + Application Interrupt and Reset Control + 0x00000D0C + + + NVIC_APINT_VECT_RESET + System Reset + [0:0] + + + NVIC_APINT_VECT_CLR_ACT + Clear Active NMI / Fault + [1:1] + + + NVIC_APINT_SYSRESETREQ + System Reset Request + [2:2] + + + NVIC_APINT_PRIGROUP + Interrupt Priority Grouping + [10:8] + + + NVIC_APINT_PRIGROUP_7_1 + Priority group 7.1 split + 0x0 + + + NVIC_APINT_PRIGROUP_6_2 + Priority group 6.2 split + 0x1 + + + NVIC_APINT_PRIGROUP_5_3 + Priority group 5.3 split + 0x2 + + + NVIC_APINT_PRIGROUP_4_4 + Priority group 4.4 split + 0x3 + + + NVIC_APINT_PRIGROUP_3_5 + Priority group 3.5 split + 0x4 + + + NVIC_APINT_PRIGROUP_2_6 + Priority group 2.6 split + 0x5 + + + NVIC_APINT_PRIGROUP_1_7 + Priority group 1.7 split + 0x6 + + + NVIC_APINT_PRIGROUP_0_8 + Priority group 0.8 split + 0x7 + + + + + NVIC_APINT_ENDIANESS + Data Endianess + [15:15] + + + NVIC_APINT_VECTKEY + Register Key + [31:16] + + + NVIC_APINT_VECTKEY + Vector key + 0x5fa + + + + + + + SYS_CTRL + System Control + 0x00000D10 + + + NVIC_SYS_CTRL_SLEEPEXIT + Sleep on ISR Exit + [1:1] + + + NVIC_SYS_CTRL_SLEEPDEEP + Deep Sleep Enable + [2:2] + + + NVIC_SYS_CTRL_SEVONPEND + Wake Up on Pending + [4:4] + + + + + CFG_CTRL + Configuration and Control + 0x00000D14 + + + NVIC_CFG_CTRL_BASE_THR + Thread State Control + [0:0] + + + NVIC_CFG_CTRL_MAIN_PEND + Allow Main Interrupt Trigger + [1:1] + + + NVIC_CFG_CTRL_UNALIGNED + Trap on Unaligned Access + [3:3] + + + NVIC_CFG_CTRL_DIV0 + Trap on Divide by 0 + [4:4] + + + NVIC_CFG_CTRL_BFHFNMIGN + Ignore Bus Fault in NMI and Fault + [8:8] + + + NVIC_CFG_CTRL_STKALIGN + Stack Alignment on Exception Entry + [9:9] + + + + + SYS_PRI1 + System Handler Priority 1 + 0x00000D18 + + + NVIC_SYS_PRI1_MEM + Memory Management Fault Priority + [7:5] + + + NVIC_SYS_PRI1_BUS + Bus Fault Priority + [15:13] + + + NVIC_SYS_PRI1_USAGE + Usage Fault Priority + [23:21] + + + + + SYS_PRI2 + System Handler Priority 2 + 0x00000D1C + + + NVIC_SYS_PRI2_SVC + SVCall Priority + [31:29] + + + + + SYS_PRI3 + System Handler Priority 3 + 0x00000D20 + + + NVIC_SYS_PRI3_DEBUG + Debug Priority + [7:5] + + + NVIC_SYS_PRI3_PENDSV + PendSV Priority + [23:21] + + + NVIC_SYS_PRI3_TICK + SysTick Exception Priority + [31:29] + + + + + SYS_HND_CTRL + System Handler Control and State + 0x00000D24 + + + NVIC_SYS_HND_CTRL_MEMA + Memory Management Fault Active + [0:0] + + + NVIC_SYS_HND_CTRL_BUSA + Bus Fault Active + [1:1] + + + NVIC_SYS_HND_CTRL_USGA + Usage Fault Active + [3:3] + + + NVIC_SYS_HND_CTRL_SVCA + SVC Call Active + [7:7] + + + NVIC_SYS_HND_CTRL_MON + Debug Monitor Active + [8:8] + + + NVIC_SYS_HND_CTRL_PNDSV + PendSV Exception Active + [10:10] + + + NVIC_SYS_HND_CTRL_TICK + SysTick Exception Active + [11:11] + + + NVIC_SYS_HND_CTRL_USAGEP + Usage Fault Pending + [12:12] + + + NVIC_SYS_HND_CTRL_MEMP + Memory Management Fault Pending + [13:13] + + + NVIC_SYS_HND_CTRL_BUSP + Bus Fault Pending + [14:14] + + + NVIC_SYS_HND_CTRL_SVC + SVC Call Pending + [15:15] + + + NVIC_SYS_HND_CTRL_MEM + Memory Management Fault Enable + [16:16] + + + NVIC_SYS_HND_CTRL_BUS + Bus Fault Enable + [17:17] + + + NVIC_SYS_HND_CTRL_USAGE + Usage Fault Enable + [18:18] + + + + + FAULT_STAT + Configurable Fault Status + 0x00000D28 + + + NVIC_FAULT_STAT_IERR + Instruction Access Violation + [0:0] + + + NVIC_FAULT_STAT_DERR + Data Access Violation + [1:1] + + + NVIC_FAULT_STAT_MUSTKE + Unstack Access Violation + [3:3] + + + NVIC_FAULT_STAT_MSTKE + Stack Access Violation + [4:4] + + + NVIC_FAULT_STAT_MMARV + Memory Management Fault Address Register Valid + [7:7] + + + NVIC_FAULT_STAT_IBUS + Instruction Bus Error + [8:8] + + + NVIC_FAULT_STAT_PRECISE + Precise Data Bus Error + [9:9] + + + NVIC_FAULT_STAT_IMPRE + Imprecise Data Bus Error + [10:10] + + + NVIC_FAULT_STAT_BUSTKE + Unstack Bus Fault + [11:11] + + + NVIC_FAULT_STAT_BSTKE + Stack Bus Fault + [12:12] + + + NVIC_FAULT_STAT_BFARV + Bus Fault Address Register Valid + [15:15] + + + NVIC_FAULT_STAT_UNDEF + Undefined Instruction Usage Fault + [16:16] + + + NVIC_FAULT_STAT_INVSTAT + Invalid State Usage Fault + [17:17] + + + NVIC_FAULT_STAT_INVPC + Invalid PC Load Usage Fault + [18:18] + + + NVIC_FAULT_STAT_NOCP + No Coprocessor Usage Fault + [19:19] + + + NVIC_FAULT_STAT_UNALIGN + Unaligned Access Usage Fault + [24:24] + + + NVIC_FAULT_STAT_DIV0 + Divide-by-Zero Usage Fault + [25:25] + + + + + HFAULT_STAT + Hard Fault Status + 0x00000D2C + + + NVIC_HFAULT_STAT_VECT + Vector Table Read Fault + [1:1] + + + NVIC_HFAULT_STAT_FORCED + Forced Hard Fault + [30:30] + + + NVIC_HFAULT_STAT_DBG + Debug Event + [31:31] + + + + + DEBUG_STAT + Debug Status Register + 0x00000D30 + + + NVIC_DEBUG_STAT_HALTED + Halt request + [0:0] + + + NVIC_DEBUG_STAT_BKPT + Breakpoint instruction + [1:1] + + + NVIC_DEBUG_STAT_DWTTRAP + DWT match + [2:2] + + + NVIC_DEBUG_STAT_VCATCH + Vector catch + [3:3] + + + NVIC_DEBUG_STAT_EXTRNL + EDBGRQ asserted + [4:4] + + + + + MM_ADDR + Memory Management Fault Address + 0x00000D34 + + + NVIC_MM_ADDR + Fault Address + [31:0] + + + + + FAULT_ADDR + Bus Fault Address + 0x00000D38 + + + NVIC_FAULT_ADDR + Fault Address + [31:0] + + + + + MPU_TYPE + MPU Type + 0x00000D90 + + + NVIC_MPU_TYPE_SEPARATE + Separate or Unified MPU + [0:0] + + + NVIC_MPU_TYPE_DREGION + Number of D Regions + [15:8] + + + NVIC_MPU_TYPE_IREGION + Number of I Regions + [23:16] + + + + + MPU_CTRL + MPU Control + 0x00000D94 + + + NVIC_MPU_CTRL_ENABLE + MPU Enable + [0:0] + + + NVIC_MPU_CTRL_HFNMIENA + MPU Enabled During Faults + [1:1] + + + NVIC_MPU_CTRL_PRIVDEFEN + MPU Default Region + [2:2] + + + + + MPU_NUMBER + MPU Region Number + 0x00000D98 + + + NVIC_MPU_NUMBER + MPU Region to Access + [2:0] + + + + + MPU_BASE + MPU Region Base Address + 0x00000D9C + + + NVIC_MPU_BASE_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR + MPU Region Attribute and Size + 0x00000DA0 + + + NVIC_MPU_ATTR_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR_SIZE_32B + Region size 32 bytes + 0x4 + + + NVIC_MPU_ATTR_SIZE_64B + Region size 64 bytes + 0x5 + + + NVIC_MPU_ATTR_SIZE_128B + Region size 128 bytes + 0x6 + + + NVIC_MPU_ATTR_SIZE_256B + Region size 256 bytes + 0x7 + + + NVIC_MPU_ATTR_SIZE_512B + Region size 512 bytes + 0x8 + + + NVIC_MPU_ATTR_SIZE_1K + Region size 1 Kbytes + 0x9 + + + NVIC_MPU_ATTR_SIZE_2K + Region size 2 Kbytes + 0xa + + + NVIC_MPU_ATTR_SIZE_4K + Region size 4 Kbytes + 0xb + + + NVIC_MPU_ATTR_SIZE_8K + Region size 8 Kbytes + 0xc + + + NVIC_MPU_ATTR_SIZE_16K + Region size 16 Kbytes + 0xd + + + NVIC_MPU_ATTR_SIZE_32K + Region size 32 Kbytes + 0xe + + + NVIC_MPU_ATTR_SIZE_64K + Region size 64 Kbytes + 0xf + + + NVIC_MPU_ATTR_SIZE_128K + Region size 128 Kbytes + 0x10 + + + NVIC_MPU_ATTR_SIZE_256K + Region size 256 Kbytes + 0x11 + + + NVIC_MPU_ATTR_SIZE_512K + Region size 512 Kbytes + 0x12 + + + NVIC_MPU_ATTR_SIZE_1M + Region size 1 Mbytes + 0x13 + + + NVIC_MPU_ATTR_SIZE_2M + Region size 2 Mbytes + 0x14 + + + NVIC_MPU_ATTR_SIZE_4M + Region size 4 Mbytes + 0x15 + + + NVIC_MPU_ATTR_SIZE_8M + Region size 8 Mbytes + 0x16 + + + NVIC_MPU_ATTR_SIZE_16M + Region size 16 Mbytes + 0x17 + + + NVIC_MPU_ATTR_SIZE_32M + Region size 32 Mbytes + 0x18 + + + NVIC_MPU_ATTR_SIZE_64M + Region size 64 Mbytes + 0x19 + + + NVIC_MPU_ATTR_SIZE_128M + Region size 128 Mbytes + 0x1a + + + NVIC_MPU_ATTR_SIZE_256M + Region size 256 Mbytes + 0x1b + + + NVIC_MPU_ATTR_SIZE_512M + Region size 512 Mbytes + 0x1c + + + NVIC_MPU_ATTR_SIZE_1G + Region size 1 Gbytes + 0x1d + + + NVIC_MPU_ATTR_SIZE_2G + Region size 2 Gbytes + 0x1e + + + NVIC_MPU_ATTR_SIZE_4G + Region size 4 Gbytes + 0x1f + + + + + NVIC_MPU_ATTR_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR_SRD_0 + Sub-region 0 disable + 0x1 + + + NVIC_MPU_ATTR_SRD_1 + Sub-region 1 disable + 0x2 + + + NVIC_MPU_ATTR_SRD_2 + Sub-region 2 disable + 0x4 + + + NVIC_MPU_ATTR_SRD_3 + Sub-region 3 disable + 0x8 + + + NVIC_MPU_ATTR_SRD_4 + Sub-region 4 disable + 0x10 + + + NVIC_MPU_ATTR_SRD_5 + Sub-region 5 disable + 0x20 + + + NVIC_MPU_ATTR_SRD_6 + Sub-region 6 disable + 0x40 + + + NVIC_MPU_ATTR_SRD_7 + Sub-region 7 disable + 0x80 + + + + + NVIC_MPU_ATTR_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR_AP_NO_NO + prv: no access, usr: no access + 0x0 + + + NVIC_MPU_ATTR_AP_RW_NO + prv: rw, usr: none + 0x1 + + + NVIC_MPU_ATTR_AP_RW_RO + prv: rw, usr: read-only + 0x2 + + + NVIC_MPU_ATTR_AP_RW_RW + prv: rw, usr: rw + 0x3 + + + NVIC_MPU_ATTR_AP_RO_NO + prv: ro, usr: none + 0x5 + + + NVIC_MPU_ATTR_AP_RO_RO + prv: ro, usr: ro + 0x6 + + + + + NVIC_MPU_ATTR_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE1 + MPU Region Base Address Alias 1 + 0x00000DA4 + + + NVIC_MPU_BASE1_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE1_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE1_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR1 + MPU Region Attribute and Size Alias 1 + 0x00000DA8 + + + NVIC_MPU_ATTR1_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR1_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR1_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR1_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR1_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR1_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR1_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR1_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR1_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE2 + MPU Region Base Address Alias 2 + 0x00000DAC + + + NVIC_MPU_BASE2_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE2_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE2_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR2 + MPU Region Attribute and Size Alias 2 + 0x00000DB0 + + + NVIC_MPU_ATTR2_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR2_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR2_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR2_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR2_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR2_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR2_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR2_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR2_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE3 + MPU Region Base Address Alias 3 + 0x00000DB4 + + + NVIC_MPU_BASE3_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE3_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE3_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR3 + MPU Region Attribute and Size Alias 3 + 0x00000DB8 + + + NVIC_MPU_ATTR3_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR3_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR3_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR3_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR3_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR3_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR3_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR3_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR3_XN + Instruction Access Disable + [28:28] + + + + + DBG_CTRL + Debug Control and Status Reg + 0x00000DF0 + + + NVIC_DBG_CTRL_C_DEBUGEN + Enable debug + [0:0] + + + NVIC_DBG_CTRL_C_HALT + Halt the core + [1:1] + + + NVIC_DBG_CTRL_C_STEP + Step the core + [2:2] + + + NVIC_DBG_CTRL_C_MASKINT + Mask interrupts when stepping + [3:3] + + + NVIC_DBG_CTRL_C_SNAPSTALL + Breaks a stalled load/store + [5:5] + + + NVIC_DBG_CTRL_S_REGRDY + Register read/write available + [16:16] + + + NVIC_DBG_CTRL_S_HALT + Core status on halt + [17:17] + + + NVIC_DBG_CTRL_S_SLEEP + Core is sleeping + [18:18] + + + NVIC_DBG_CTRL_S_LOCKUP + Core is locked up + [19:19] + + + NVIC_DBG_CTRL_S_RETIRE_ST + Core has executed insruction since last read + [24:24] + + + NVIC_DBG_CTRL_S_RESET_ST + Core has reset since last read + [25:25] + + + + + DBG_XFER + Debug Core Reg. Transfer Select + 0x00000DF4 + + + NVIC_DBG_XFER_REG_SEL + Register + [4:0] + + + NVIC_DBG_XFER_REG_R0 + Register R0 + 0x0 + + + NVIC_DBG_XFER_REG_R1 + Register R1 + 0x1 + + + NVIC_DBG_XFER_REG_R2 + Register R2 + 0x2 + + + NVIC_DBG_XFER_REG_R3 + Register R3 + 0x3 + + + NVIC_DBG_XFER_REG_R4 + Register R4 + 0x4 + + + NVIC_DBG_XFER_REG_R5 + Register R5 + 0x5 + + + NVIC_DBG_XFER_REG_R6 + Register R6 + 0x6 + + + NVIC_DBG_XFER_REG_R7 + Register R7 + 0x7 + + + NVIC_DBG_XFER_REG_R8 + Register R8 + 0x8 + + + NVIC_DBG_XFER_REG_R9 + Register R9 + 0x9 + + + NVIC_DBG_XFER_REG_R10 + Register R10 + 0xa + + + NVIC_DBG_XFER_REG_R11 + Register R11 + 0xb + + + NVIC_DBG_XFER_REG_R12 + Register R12 + 0xc + + + NVIC_DBG_XFER_REG_R13 + Register R13 + 0xd + + + NVIC_DBG_XFER_REG_R14 + Register R14 + 0xe + + + NVIC_DBG_XFER_REG_R15 + Register R15 + 0xf + + + NVIC_DBG_XFER_REG_FLAGS + xPSR/Flags register + 0x10 + + + NVIC_DBG_XFER_REG_MSP + Main SP + 0x11 + + + NVIC_DBG_XFER_REG_PSP + Process SP + 0x12 + + + NVIC_DBG_XFER_REG_DSP + Deep SP + 0x13 + + + NVIC_DBG_XFER_REG_CFBP + Control/Fault/BasePri/PriMask + 0x14 + + + + + NVIC_DBG_XFER_REG_WNR + Write or not read + [16:16] + + + + + DBG_DATA + Debug Core Register Data + 0x00000DF8 + + + NVIC_DBG_DATA + Data temporary cache + [31:0] + + + + + DBG_INT + Debug Reset Interrupt Control + 0x00000DFC + + + NVIC_DBG_INT_RSTVCATCH + Reset vector catch + [0:0] + + + NVIC_DBG_INT_RSTPENDING + Core reset is pending + [1:1] + + + NVIC_DBG_INT_RSTPENDCLR + Clear pending core reset + [2:2] + + + NVIC_DBG_INT_RESET + Core reset status + [3:3] + + + NVIC_DBG_INT_MMERR + Debug trap on mem manage fault + [4:4] + + + NVIC_DBG_INT_NOCPERR + Debug trap on coprocessor error + [5:5] + + + NVIC_DBG_INT_CHKERR + Debug trap on usage fault check + [6:6] + + + NVIC_DBG_INT_STATERR + Debug trap on usage fault state + [7:7] + + + NVIC_DBG_INT_BUSERR + Debug trap on bus error + [8:8] + + + NVIC_DBG_INT_INTERR + Debug trap on interrupt errors + [9:9] + + + NVIC_DBG_INT_HARDERR + Debug trap on hard fault + [10:10] + + + + + SW_TRIG + Software Trigger Interrupt + 0x00000F00 + write-only + + + NVIC_SW_TRIG_INTID + Interrupt ID + [5:0] + write-only + + + + + + + + + FLASH + FLASH Memory Map for lm3s6965 + 0x00000000 + + 0 + 0x00040000 + FLASH Memory + + + + SRAM + SRAM Memory Map for lm3s6965 + 0x20000000 + + 0 + 0x00010000 + SRAM + + + + diff --git a/svd/lm3s811.svd b/svd/lm3s811.svd new file mode 100644 index 0000000..fc773a8 --- /dev/null +++ b/svd/lm3s811.svd @@ -0,0 +1,8492 @@ + + + + LM3S811 + 7944 + ARM Cortex-M3 Stellaris Device + 8 + 32 + 32 + read-write + 0 + 0 + + + WATCHDOG0 + Register map for WATCHDOG0 peripheral + WATCHDOG + WATCHDOG0 + 0x40000000 + + 0 + 0x00001000 + registers + + + + LOAD + Watchdog Load + 0x00000000 + + + WDT_LOAD + Watchdog Load Value + [31:0] + + + + + VALUE + Watchdog Value + 0x00000004 + + + WDT_VALUE + Watchdog Value + [31:0] + + + + + CTL + Watchdog Control + 0x00000008 + + + WDT_CTL_INTEN + Watchdog Interrupt Enable + [0:0] + + + WDT_CTL_RESEN + Watchdog Reset Enable + [1:1] + + + + + ICR + Watchdog Interrupt Clear + 0x0000000C + write-only + + + WDT_ICR + Watchdog Interrupt Clear + [31:0] + write-only + + + + + RIS + Watchdog Raw Interrupt Status + 0x00000010 + + + WDT_RIS_WDTRIS + Watchdog Raw Interrupt Status + [0:0] + + + + + MIS + Watchdog Masked Interrupt Status + 0x00000014 + + + WDT_MIS_WDTMIS + Watchdog Masked Interrupt Status + [0:0] + + + + + TEST + Watchdog Test + 0x00000418 + + + WDT_TEST_STALL + Watchdog Stall Enable + [8:8] + + + + + LOCK + Watchdog Lock + 0x00000C00 + + + WDT_LOCK + Watchdog Lock + [31:0] + + + WDT_LOCK_UNLOCKED + Unlocked + 0x0 + + + WDT_LOCK_LOCKED + Locked + 0x1 + + + WDT_LOCK_UNLOCK + Unlocks the watchdog timer + 0x1acce551 + + + + + + + + + GPIO_PORTA + Register map for GPIO_PORTA peripheral + GPIO_PORT + GPIO_PORTA + 0x40004000 + + 0 + 0x00001000 + registers + + + + DATA + GPIO Data + 0x000003FC + + + DIR + GPIO Direction + 0x00000400 + + + IS + GPIO Interrupt Sense + 0x00000404 + + + IBE + GPIO Interrupt Both Edges + 0x00000408 + + + IEV + GPIO Interrupt Event + 0x0000040C + + + IM + GPIO Interrupt Mask + 0x00000410 + + + RIS + GPIO Raw Interrupt Status + 0x00000414 + + + MIS + GPIO Masked Interrupt Status + 0x00000418 + + + ICR + GPIO Interrupt Clear + 0x0000041C + write-only + + + AFSEL + GPIO Alternate Function Select + 0x00000420 + + + DR2R + GPIO 2-mA Drive Select + 0x00000500 + + + DR4R + GPIO 4-mA Drive Select + 0x00000504 + + + DR8R + GPIO 8-mA Drive Select + 0x00000508 + + + ODR + GPIO Open Drain Select + 0x0000050C + + + PUR + GPIO Pull-Up Select + 0x00000510 + + + PDR + GPIO Pull-Down Select + 0x00000514 + + + SLR + GPIO Slew Rate Control Select + 0x00000518 + + + DEN + GPIO Digital Enable + 0x0000051C + + + + + GPIO_PORTB + GPIO_PORTB + 0x40005000 + + + GPIO_PORTC + GPIO_PORTC + 0x40006000 + + + GPIO_PORTD + GPIO_PORTD + 0x40007000 + + + SSI0 + Register map for SSI0 peripheral + SSI + SSI0 + 0x40008000 + + 0 + 0x00001000 + registers + + + + CR0 + SSI Control 0 + 0x00000000 + + + SSI_CR0_DSS + SSI Data Size Select + [3:0] + + + SSI_CR0_DSS_4 + 4-bit data + 0x3 + + + SSI_CR0_DSS_5 + 5-bit data + 0x4 + + + SSI_CR0_DSS_6 + 6-bit data + 0x5 + + + SSI_CR0_DSS_7 + 7-bit data + 0x6 + + + SSI_CR0_DSS_8 + 8-bit data + 0x7 + + + SSI_CR0_DSS_9 + 9-bit data + 0x8 + + + SSI_CR0_DSS_10 + 10-bit data + 0x9 + + + SSI_CR0_DSS_11 + 11-bit data + 0xa + + + SSI_CR0_DSS_12 + 12-bit data + 0xb + + + SSI_CR0_DSS_13 + 13-bit data + 0xc + + + SSI_CR0_DSS_14 + 14-bit data + 0xd + + + SSI_CR0_DSS_15 + 15-bit data + 0xe + + + SSI_CR0_DSS_16 + 16-bit data + 0xf + + + + + SSI_CR0_FRF + SSI Frame Format Select + [5:4] + + + SSI_CR0_FRF_MOTO + Freescale SPI Frame Format + 0x0 + + + SSI_CR0_FRF_TI + Texas Instruments Synchronous Serial Frame Format + 0x1 + + + SSI_CR0_FRF_NMW + MICROWIRE Frame Format + 0x2 + + + + + SSI_CR0_SPO + SSI Serial Clock Polarity + [6:6] + + + SSI_CR0_SPH + SSI Serial Clock Phase + [7:7] + + + SSI_CR0_SCR + SSI Serial Clock Rate + [15:8] + + + + + CR1 + SSI Control 1 + 0x00000004 + + + SSI_CR1_LBM + SSI Loopback Mode + [0:0] + + + SSI_CR1_SSE + SSI Synchronous Serial Port Enable + [1:1] + + + SSI_CR1_MS + SSI Master/Slave Select + [2:2] + + + SSI_CR1_SOD + SSI Slave Mode Output Disable + [3:3] + + + + + DR + SSI Data + 0x00000008 + + + SSI_DR_DATA + SSI Receive/Transmit Data + [15:0] + + + + + SR + SSI Status + 0x0000000C + + + SSI_SR_TFE + SSI Transmit FIFO Empty + [0:0] + + + SSI_SR_TNF + SSI Transmit FIFO Not Full + [1:1] + + + SSI_SR_RNE + SSI Receive FIFO Not Empty + [2:2] + + + SSI_SR_RFF + SSI Receive FIFO Full + [3:3] + + + SSI_SR_BSY + SSI Busy Bit + [4:4] + + + + + CPSR + SSI Clock Prescale + 0x00000010 + + + SSI_CPSR_CPSDVSR + SSI Clock Prescale Divisor + [7:0] + + + + + IM + SSI Interrupt Mask + 0x00000014 + + + SSI_IM_RORIM + SSI Receive Overrun Interrupt Mask + [0:0] + + + SSI_IM_RTIM + SSI Receive Time-Out Interrupt Mask + [1:1] + + + SSI_IM_RXIM + SSI Receive FIFO Interrupt Mask + [2:2] + + + SSI_IM_TXIM + SSI Transmit FIFO Interrupt Mask + [3:3] + + + + + RIS + SSI Raw Interrupt Status + 0x00000018 + + + SSI_RIS_RORRIS + SSI Receive Overrun Raw Interrupt Status + [0:0] + + + SSI_RIS_RTRIS + SSI Receive Time-Out Raw Interrupt Status + [1:1] + + + SSI_RIS_RXRIS + SSI Receive FIFO Raw Interrupt Status + [2:2] + + + SSI_RIS_TXRIS + SSI Transmit FIFO Raw Interrupt Status + [3:3] + + + + + MIS + SSI Masked Interrupt Status + 0x0000001C + + + SSI_MIS_RORMIS + SSI Receive Overrun Masked Interrupt Status + [0:0] + + + SSI_MIS_RTMIS + SSI Receive Time-Out Masked Interrupt Status + [1:1] + + + SSI_MIS_RXMIS + SSI Receive FIFO Masked Interrupt Status + [2:2] + + + SSI_MIS_TXMIS + SSI Transmit FIFO Masked Interrupt Status + [3:3] + + + + + ICR + SSI Interrupt Clear + 0x00000020 + write-only + + + SSI_ICR_RORIC + SSI Receive Overrun Interrupt Clear + [0:0] + write-only + + + SSI_ICR_RTIC + SSI Receive Time-Out Interrupt Clear + [1:1] + write-only + + + + + + + UART0 + Register map for UART0 peripheral + UART + UART0 + 0x4000C000 + + 0 + 0x00001000 + registers + + + + DR + UART Data + 0x00000000 + + + UART_DR_DATA + Data Transmitted or Received + [7:0] + + + UART_DR_FE + UART Framing Error + [8:8] + + + UART_DR_PE + UART Parity Error + [9:9] + + + UART_DR_BE + UART Break Error + [10:10] + + + UART_DR_OE + UART Overrun Error + [11:11] + + + + + RSR + UART Receive Status/Error Clear + 0x00000004 + + + UART_RSR_FE + UART Framing Error + [0:0] + + + UART_RSR_PE + UART Parity Error + [1:1] + + + UART_RSR_BE + UART Break Error + [2:2] + + + UART_RSR_OE + UART Overrun Error + [3:3] + + + + + ECR + UART Receive Status/Error Clear + UART_ALT + 0x00000004 + + + UART_ECR_DATA + Error Clear + [7:0] + + + + + FR + UART Flag + 0x00000018 + + + UART_FR_BUSY + UART Busy + [3:3] + + + UART_FR_RXFE + UART Receive FIFO Empty + [4:4] + + + UART_FR_TXFF + UART Transmit FIFO Full + [5:5] + + + UART_FR_RXFF + UART Receive FIFO Full + [6:6] + + + UART_FR_TXFE + UART Transmit FIFO Empty + [7:7] + + + + + IBRD + UART Integer Baud-Rate Divisor + 0x00000024 + + + UART_IBRD_DIVINT + Integer Baud-Rate Divisor + [15:0] + + + + + FBRD + UART Fractional Baud-Rate Divisor + 0x00000028 + + + UART_FBRD_DIVFRAC + Fractional Baud-Rate Divisor + [5:0] + + + + + LCRH + UART Line Control + 0x0000002C + + + UART_LCRH_BRK + UART Send Break + [0:0] + + + UART_LCRH_PEN + UART Parity Enable + [1:1] + + + UART_LCRH_EPS + UART Even Parity Select + [2:2] + + + UART_LCRH_STP2 + UART Two Stop Bits Select + [3:3] + + + UART_LCRH_FEN + UART Enable FIFOs + [4:4] + + + UART_LCRH_WLEN + UART Word Length + [6:5] + + + UART_LCRH_WLEN_5 + 5 bits (default) + 0x0 + + + UART_LCRH_WLEN_6 + 6 bits + 0x1 + + + UART_LCRH_WLEN_7 + 7 bits + 0x2 + + + UART_LCRH_WLEN_8 + 8 bits + 0x3 + + + + + UART_LCRH_SPS + UART Stick Parity Select + [7:7] + + + + + CTL + UART Control + 0x00000030 + + + UART_CTL_UARTEN + UART Enable + [0:0] + + + UART_CTL_LBE + UART Loop Back Enable + [7:7] + + + UART_CTL_TXE + UART Transmit Enable + [8:8] + + + UART_CTL_RXE + UART Receive Enable + [9:9] + + + + + IFLS + UART Interrupt FIFO Level Select + 0x00000034 + + + UART_IFLS_TX + UART Transmit Interrupt FIFO Level Select + [2:0] + + + UART_IFLS_TX1_8 + TX FIFO &lt;= 1/8 full + 0x0 + + + UART_IFLS_TX2_8 + TX FIFO &lt;= 1/4 full + 0x1 + + + UART_IFLS_TX4_8 + TX FIFO &lt;= 1/2 full (default) + 0x2 + + + UART_IFLS_TX6_8 + TX FIFO &lt;= 3/4 full + 0x3 + + + UART_IFLS_TX7_8 + TX FIFO &lt;= 7/8 full + 0x4 + + + + + UART_IFLS_RX + UART Receive Interrupt FIFO Level Select + [5:3] + + + UART_IFLS_RX1_8 + RX FIFO >= 1/8 full + 0x0 + + + UART_IFLS_RX2_8 + RX FIFO >= 1/4 full + 0x1 + + + UART_IFLS_RX4_8 + RX FIFO >= 1/2 full (default) + 0x2 + + + UART_IFLS_RX6_8 + RX FIFO >= 3/4 full + 0x3 + + + UART_IFLS_RX7_8 + RX FIFO >= 7/8 full + 0x4 + + + + + + + IM + UART Interrupt Mask + 0x00000038 + + + UART_IM_RXIM + UART Receive Interrupt Mask + [4:4] + + + UART_IM_TXIM + UART Transmit Interrupt Mask + [5:5] + + + UART_IM_RTIM + UART Receive Time-Out Interrupt Mask + [6:6] + + + UART_IM_FEIM + UART Framing Error Interrupt Mask + [7:7] + + + UART_IM_PEIM + UART Parity Error Interrupt Mask + [8:8] + + + UART_IM_BEIM + UART Break Error Interrupt Mask + [9:9] + + + UART_IM_OEIM + UART Overrun Error Interrupt Mask + [10:10] + + + + + RIS + UART Raw Interrupt Status + 0x0000003C + + + UART_RIS_RXRIS + UART Receive Raw Interrupt Status + [4:4] + + + UART_RIS_TXRIS + UART Transmit Raw Interrupt Status + [5:5] + + + UART_RIS_RTRIS + UART Receive Time-Out Raw Interrupt Status + [6:6] + + + UART_RIS_FERIS + UART Framing Error Raw Interrupt Status + [7:7] + + + UART_RIS_PERIS + UART Parity Error Raw Interrupt Status + [8:8] + + + UART_RIS_BERIS + UART Break Error Raw Interrupt Status + [9:9] + + + UART_RIS_OERIS + UART Overrun Error Raw Interrupt Status + [10:10] + + + + + MIS + UART Masked Interrupt Status + 0x00000040 + + + UART_MIS_RXMIS + UART Receive Masked Interrupt Status + [4:4] + + + UART_MIS_TXMIS + UART Transmit Masked Interrupt Status + [5:5] + + + UART_MIS_RTMIS + UART Receive Time-Out Masked Interrupt Status + [6:6] + + + UART_MIS_FEMIS + UART Framing Error Masked Interrupt Status + [7:7] + + + UART_MIS_PEMIS + UART Parity Error Masked Interrupt Status + [8:8] + + + UART_MIS_BEMIS + UART Break Error Masked Interrupt Status + [9:9] + + + UART_MIS_OEMIS + UART Overrun Error Masked Interrupt Status + [10:10] + + + + + ICR + UART Interrupt Clear + 0x00000044 + write-only + + + UART_ICR_RXIC + Receive Interrupt Clear + [4:4] + write-only + + + UART_ICR_TXIC + Transmit Interrupt Clear + [5:5] + write-only + + + UART_ICR_RTIC + Receive Time-Out Interrupt Clear + [6:6] + write-only + + + UART_ICR_FEIC + Framing Error Interrupt Clear + [7:7] + write-only + + + UART_ICR_PEIC + Parity Error Interrupt Clear + [8:8] + write-only + + + UART_ICR_BEIC + Break Error Interrupt Clear + [9:9] + write-only + + + UART_ICR_OEIC + Overrun Error Interrupt Clear + [10:10] + write-only + + + + + + + UART1 + UART1 + 0x4000D000 + + + I2C0 + Register map for I2C0 peripheral + I2C + I2C0 + 0x40020000 + + 0 + 0x00001000 + registers + + + + MSA + I2C Master Slave Address + 0x00000000 + + + I2C_MSA_RS + Receive not send + [0:0] + + + I2C_MSA_SA + I2C Slave Address + [7:1] + + + + + SOAR + I2C Slave Own Address + 0x00000800 + + + I2C_SOAR_OAR + I2C Slave Own Address + [6:0] + + + + + SCSR + I2C Slave Control/Status + 0x00000804 + + + I2C_SCSR_RREQ + Receive Request + [0:0] + + + I2C_SCSR_TREQ + Transmit Request + [1:1] + + + I2C_SCSR_FBR + First Byte Received + [2:2] + + + + + SCSR + I2C Slave Control/Status + I2C0_ALT + 0x00000804 + + + I2C_SCSR_DA + Device Active + [0:0] + + + + + MCS + I2C Master Control/Status + 0x00000004 + + + I2C_MCS_RUN + I2C Master Enable + [0:0] + + + I2C_MCS_START + Generate START + [1:1] + + + I2C_MCS_ADRACK + Acknowledge Address + [2:2] + + + I2C_MCS_ACK + Data Acknowledge Enable + [3:3] + + + I2C_MCS_ARBLST + Arbitration Lost + [4:4] + + + I2C_MCS_IDLE + I2C Idle + [5:5] + + + I2C_MCS_BUSBSY + Bus Busy + [6:6] + + + + + MCS + I2C Master Control/Status + I2C0_ALT + 0x00000004 + + + I2C_MCS_BUSY + I2C Busy + [0:0] + + + I2C_MCS_ERROR + Error + [1:1] + + + I2C_MCS_STOP + Generate STOP + [2:2] + + + I2C_MCS_DATACK + Acknowledge Data + [3:3] + + + + + SDR + I2C Slave Data + 0x00000808 + + + I2C_SDR_DATA + Data for Transfer + [7:0] + + + + + MDR + I2C Master Data + 0x00000008 + + + I2C_MDR_DATA + Data Transferred + [7:0] + + + + + MTPR + I2C Master Timer Period + 0x0000000C + + + I2C_MTPR_TPR + SCL Clock Period + [6:0] + + + + + SIMR + I2C Slave Interrupt Mask + 0x0000080C + + + I2C_SIMR_DATAIM + Data Interrupt Mask + [0:0] + + + + + SRIS + I2C Slave Raw Interrupt Status + 0x00000810 + + + I2C_SRIS_DATARIS + Data Raw Interrupt Status + [0:0] + + + + + MIMR + I2C Master Interrupt Mask + 0x00000010 + + + I2C_MIMR_IM + Interrupt Mask + [0:0] + + + + + MRIS + I2C Master Raw Interrupt Status + 0x00000014 + + + I2C_MRIS_RIS + Raw Interrupt Status + [0:0] + + + + + SMIS + I2C Slave Masked Interrupt Status + 0x00000814 + + + I2C_SMIS_DATAMIS + Data Masked Interrupt Status + [0:0] + + + + + SICR + I2C Slave Interrupt Clear + 0x00000818 + write-only + + + I2C_SICR_DATAIC + Data Interrupt Clear + [0:0] + write-only + + + + + MMIS + I2C Master Masked Interrupt Status + 0x00000018 + + + I2C_MMIS_MIS + Masked Interrupt Status + [0:0] + + + + + MICR + I2C Master Interrupt Clear + 0x0000001C + write-only + + + I2C_MICR_IC + Interrupt Clear + [0:0] + write-only + + + + + MCR + I2C Master Configuration + 0x00000020 + + + I2C_MCR_LPBK + I2C Loopback + [0:0] + + + I2C_MCR_MFE + I2C Master Function Enable + [4:4] + + + I2C_MCR_SFE + I2C Slave Function Enable + [5:5] + + + + + + + GPIO_PORTE + GPIO_PORTE + 0x40024000 + + + PWM0 + Register map for PWM0 peripheral + PWM + PWM0 + 0x40028000 + + 0 + 0x00001000 + registers + + + + CTL + PWM Master Control + 0x00000000 + + + PWM_CTL_GLOBALSYNC0 + Update PWM Generator 0 + [0:0] + + + PWM_CTL_GLOBALSYNC1 + Update PWM Generator 1 + [1:1] + + + PWM_CTL_GLOBALSYNC2 + Update PWM Generator 2 + [2:2] + + + + + SYNC + PWM Time Base Sync + 0x00000004 + + + PWM_SYNC_SYNC0 + Reset Generator 0 Counter + [0:0] + + + PWM_SYNC_SYNC1 + Reset Generator 1 Counter + [1:1] + + + PWM_SYNC_SYNC2 + Reset Generator 2 Counter + [2:2] + + + + + ENABLE + PWM Output Enable + 0x00000008 + + + PWM_ENABLE_PWM0EN + PWM0 Output Enable + [0:0] + + + PWM_ENABLE_PWM1EN + PWM1 Output Enable + [1:1] + + + PWM_ENABLE_PWM2EN + PWM2 Output Enable + [2:2] + + + PWM_ENABLE_PWM3EN + PWM3 Output Enable + [3:3] + + + PWM_ENABLE_PWM4EN + PWM4 Output Enable + [4:4] + + + PWM_ENABLE_PWM5EN + PWM5 Output Enable + [5:5] + + + + + INVERT + PWM Output Inversion + 0x0000000C + + + PWM_INVERT_PWM0INV + Invert PWM0 Signal + [0:0] + + + PWM_INVERT_PWM1INV + Invert PWM1 Signal + [1:1] + + + PWM_INVERT_PWM2INV + Invert PWM2 Signal + [2:2] + + + PWM_INVERT_PWM3INV + Invert PWM3 Signal + [3:3] + + + PWM_INVERT_PWM4INV + Invert PWM4 Signal + [4:4] + + + PWM_INVERT_PWM5INV + Invert PWM5 Signal + [5:5] + + + + + FAULT + PWM Output Fault + 0x00000010 + + + PWM_FAULT_FAULT0 + PWM0 Fault + [0:0] + + + PWM_FAULT_FAULT1 + PWM1 Fault + [1:1] + + + PWM_FAULT_FAULT2 + PWM2 Fault + [2:2] + + + PWM_FAULT_FAULT3 + PWM3 Fault + [3:3] + + + PWM_FAULT_FAULT4 + PWM4 Fault + [4:4] + + + PWM_FAULT_FAULT5 + PWM5 Fault + [5:5] + + + + + INTEN + PWM Interrupt Enable + 0x00000014 + + + PWM_INTEN_INTPWM0 + PWM0 Interrupt Enable + [0:0] + + + PWM_INTEN_INTPWM1 + PWM1 Interrupt Enable + [1:1] + + + PWM_INTEN_INTPWM2 + PWM2 Interrupt Enable + [2:2] + + + PWM_INTEN_INTFAULT + Fault Interrupt Enable + [16:16] + + + + + RIS + PWM Raw Interrupt Status + 0x00000018 + + + PWM_RIS_INTPWM0 + PWM0 Interrupt Asserted + [0:0] + + + PWM_RIS_INTPWM1 + PWM1 Interrupt Asserted + [1:1] + + + PWM_RIS_INTPWM2 + PWM2 Interrupt Asserted + [2:2] + + + PWM_RIS_INTFAULT + Fault Interrupt Asserted + [16:16] + + + + + ISC + PWM Interrupt Status and Clear + 0x0000001C + + + PWM_ISC_INTPWM0 + PWM0 Interrupt Status + [0:0] + + + PWM_ISC_INTPWM1 + PWM1 Interrupt Status + [1:1] + + + PWM_ISC_INTPWM2 + PWM2 Interrupt Status + [2:2] + + + PWM_ISC_INTFAULT + Fault Interrupt Asserted + [16:16] + + + + + STATUS + PWM Status + 0x00000020 + + + _0_CTL + PWM0 Control + 0x00000040 + + + PWM_X_CTL_ENABLE + PWM Block Enable + [0:0] + + + PWM_X_CTL_MODE + Counter Mode + [1:1] + + + PWM_X_CTL_DEBUG + Debug Mode + [2:2] + + + PWM_X_CTL_LOADUPD + Load Register Update Mode + [3:3] + + + PWM_X_CTL_CMPAUPD + Comparator A Update Mode + [4:4] + + + PWM_X_CTL_CMPBUPD + Comparator B Update Mode + [5:5] + + + + + _0_INTEN + PWM0 Interrupt and Trigger Enable + 0x00000044 + + + PWM_X_INTEN_INTCNTZERO + Interrupt for Counter=0 + [0:0] + + + PWM_X_INTEN_INTCNTLOAD + Interrupt for Counter=PWMnLOAD + [1:1] + + + PWM_X_INTEN_INTCMPAU + Interrupt for Counter=PWMnCMPA Up + [2:2] + + + PWM_X_INTEN_INTCMPAD + Interrupt for Counter=PWMnCMPA Down + [3:3] + + + PWM_X_INTEN_INTCMPBU + Interrupt for Counter=PWMnCMPB Up + [4:4] + + + PWM_X_INTEN_INTCMPBD + Interrupt for Counter=PWMnCMPB Down + [5:5] + + + PWM_X_INTEN_TRCNTZERO + Trigger for Counter=0 + [8:8] + + + PWM_X_INTEN_TRCNTLOAD + Trigger for Counter=PWMnLOAD + [9:9] + + + PWM_X_INTEN_TRCMPAU + Trigger for Counter=PWMnCMPA Up + [10:10] + + + PWM_X_INTEN_TRCMPAD + Trigger for Counter=PWMnCMPA Down + [11:11] + + + PWM_X_INTEN_TRCMPBU + Trigger for Counter=PWMnCMPB Up + [12:12] + + + PWM_X_INTEN_TRCMPBD + Trigger for Counter=PWMnCMPB Down + [13:13] + + + + + _0_RIS + PWM0 Raw Interrupt Status + 0x00000048 + + + PWM_X_RIS_INTCNTZERO + Counter=0 Interrupt Status + [0:0] + + + PWM_X_RIS_INTCNTLOAD + Counter=Load Interrupt Status + [1:1] + + + PWM_X_RIS_INTCMPAU + Comparator A Up Interrupt Status + [2:2] + + + PWM_X_RIS_INTCMPAD + Comparator A Down Interrupt Status + [3:3] + + + PWM_X_RIS_INTCMPBU + Comparator B Up Interrupt Status + [4:4] + + + PWM_X_RIS_INTCMPBD + Comparator B Down Interrupt Status + [5:5] + + + + + _0_ISC + PWM0 Interrupt Status and Clear + 0x0000004C + + + PWM_X_ISC_INTCNTZERO + Counter=0 Interrupt + [0:0] + + + PWM_X_ISC_INTCNTLOAD + Counter=Load Interrupt + [1:1] + + + PWM_X_ISC_INTCMPAU + Comparator A Up Interrupt + [2:2] + + + PWM_X_ISC_INTCMPAD + Comparator A Down Interrupt + [3:3] + + + PWM_X_ISC_INTCMPBU + Comparator B Up Interrupt + [4:4] + + + PWM_X_ISC_INTCMPBD + Comparator B Down Interrupt + [5:5] + + + + + _0_LOAD + PWM0 Load + 0x00000050 + + + PWM_X_LOAD + Counter Load Value + [15:0] + + + + + _0_COUNT + PWM0 Counter + 0x00000054 + + + PWM_X_COUNT + Counter Value + [15:0] + + + + + _0_CMPA + PWM0 Compare A + 0x00000058 + + + PWM_X_CMPA + Comparator A Value + [15:0] + + + + + _0_CMPB + PWM0 Compare B + 0x0000005C + + + PWM_X_CMPB + Comparator B Value + [15:0] + + + + + _0_GENA + PWM0 Generator A Control + 0x00000060 + + + PWM_X_GENA_ACTZERO + Action for Counter=0 + [1:0] + + + PWM_X_GENA_ACTZERO_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTZERO_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTZERO_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTZERO_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTLOAD + Action for Counter=LOAD + [3:2] + + + PWM_X_GENA_ACTLOAD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTLOAD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTLOAD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTLOAD_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPAU + Action for Comparator A Up + [5:4] + + + PWM_X_GENA_ACTCMPAU_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPAU_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPAU_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPAU_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPAD + Action for Comparator A Down + [7:6] + + + PWM_X_GENA_ACTCMPAD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPAD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPAD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPAD_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPBU + Action for Comparator B Up + [9:8] + + + PWM_X_GENA_ACTCMPBU_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPBU_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPBU_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPBU_ONE + Drive pwmA High + 0x3 + + + + + PWM_X_GENA_ACTCMPBD + Action for Comparator B Down + [11:10] + + + PWM_X_GENA_ACTCMPBD_NONE + Do nothing + 0x0 + + + PWM_X_GENA_ACTCMPBD_INV + Invert pwmA + 0x1 + + + PWM_X_GENA_ACTCMPBD_ZERO + Drive pwmA Low + 0x2 + + + PWM_X_GENA_ACTCMPBD_ONE + Drive pwmA High + 0x3 + + + + + + + _0_GENB + PWM0 Generator B Control + 0x00000064 + + + PWM_X_GENB_ACTZERO + Action for Counter=0 + [1:0] + + + PWM_X_GENB_ACTZERO_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTZERO_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTZERO_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTZERO_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTLOAD + Action for Counter=LOAD + [3:2] + + + PWM_X_GENB_ACTLOAD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTLOAD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTLOAD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTLOAD_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPAU + Action for Comparator A Up + [5:4] + + + PWM_X_GENB_ACTCMPAU_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPAU_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPAU_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPAU_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPAD + Action for Comparator A Down + [7:6] + + + PWM_X_GENB_ACTCMPAD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPAD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPAD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPAD_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPBU + Action for Comparator B Up + [9:8] + + + PWM_X_GENB_ACTCMPBU_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPBU_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPBU_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPBU_ONE + Drive pwmB High + 0x3 + + + + + PWM_X_GENB_ACTCMPBD + Action for Comparator B Down + [11:10] + + + PWM_X_GENB_ACTCMPBD_NONE + Do nothing + 0x0 + + + PWM_X_GENB_ACTCMPBD_INV + Invert pwmB + 0x1 + + + PWM_X_GENB_ACTCMPBD_ZERO + Drive pwmB Low + 0x2 + + + PWM_X_GENB_ACTCMPBD_ONE + Drive pwmB High + 0x3 + + + + + + + _0_DBCTL + PWM0 Dead-Band Control + 0x00000068 + + + PWM_X_DBCTL_ENABLE + Dead-Band Generator Enable + [0:0] + + + + + _0_DBRISE + PWM0 Dead-Band Rising-Edge Delay + 0x0000006C + + + PWM_X_DBRISE_DELAY + Dead-Band Rise Delay + [11:0] + + + + + _0_DBFALL + PWM0 Dead-Band Falling-Edge-Delay + 0x00000070 + + + PWM_X_DBFALL_DELAY + Dead-Band Fall Delay + [11:0] + + + + + _1_CTL + PWM1 Control + 0x00000080 + + + _1_INTEN + PWM1 Interrupt and Trigger Enable + 0x00000084 + + + _1_RIS + PWM1 Raw Interrupt Status + 0x00000088 + + + _1_ISC + PWM1 Interrupt Status and Clear + 0x0000008C + + + _1_LOAD + PWM1 Load + 0x00000090 + + + _1_COUNT + PWM1 Counter + 0x00000094 + + + _1_CMPA + PWM1 Compare A + 0x00000098 + + + _1_CMPB + PWM1 Compare B + 0x0000009C + + + _1_GENA + PWM1 Generator A Control + 0x000000A0 + + + _1_GENB + PWM1 Generator B Control + 0x000000A4 + + + _1_DBCTL + PWM1 Dead-Band Control + 0x000000A8 + + + _1_DBRISE + PWM1 Dead-Band Rising-Edge Delay + 0x000000AC + + + _1_DBFALL + PWM1 Dead-Band Falling-Edge-Delay + 0x000000B0 + + + _2_CTL + PWM2 Control + 0x000000C0 + + + _2_INTEN + PWM2 Interrupt and Trigger Enable + 0x000000C4 + + + _2_RIS + PWM2 Raw Interrupt Status + 0x000000C8 + + + _2_ISC + PWM2 Interrupt Status and Clear + 0x000000CC + + + _2_LOAD + PWM2 Load + 0x000000D0 + + + _2_COUNT + PWM2 Counter + 0x000000D4 + + + _2_CMPA + PWM2 Compare A + 0x000000D8 + + + _2_CMPB + PWM2 Compare B + 0x000000DC + + + _2_GENA + PWM2 Generator A Control + 0x000000E0 + + + _2_GENB + PWM2 Generator B Control + 0x000000E4 + + + _2_DBCTL + PWM2 Dead-Band Control + 0x000000E8 + + + _2_DBRISE + PWM2 Dead-Band Rising-Edge Delay + 0x000000EC + + + _2_DBFALL + PWM2 Dead-Band Falling-Edge-Delay + 0x000000F0 + + + + + TIMER0 + Register map for TIMER0 peripheral + TIMER + TIMER0 + 0x40030000 + + 0 + 0x00001000 + registers + + + + CFG + GPTM Configuration + 0x00000000 + + + TIMER_CFG + GPTM Configuration + [2:0] + + + TIMER_CFG_32_BIT_TIMER + 32-bit timer configuration + 0x0 + + + TIMER_CFG_32_BIT_RTC + 32-bit real-time clock (RTC) counter configuration + 0x1 + + + TIMER_CFG_16_BIT + 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR + 0x4 + + + + + + + TAMR + GPTM Timer A Mode + 0x00000004 + + + TIMER_TAMR_TAMR + GPTM Timer A Mode + [1:0] + + + TIMER_TAMR_TAMR_1_SHOT + One-Shot Timer mode + 0x1 + + + TIMER_TAMR_TAMR_PERIOD + Periodic Timer mode + 0x2 + + + TIMER_TAMR_TAMR_CAP + Capture mode + 0x3 + + + + + TIMER_TAMR_TACMR + GPTM Timer A Capture Mode + [2:2] + + + TIMER_TAMR_TAAMS + GPTM Timer A Alternate Mode Select + [3:3] + + + + + TBMR + GPTM Timer B Mode + 0x00000008 + + + TIMER_TBMR_TBMR + GPTM Timer B Mode + [1:0] + + + TIMER_TBMR_TBMR_1_SHOT + One-Shot Timer mode + 0x1 + + + TIMER_TBMR_TBMR_PERIOD + Periodic Timer mode + 0x2 + + + TIMER_TBMR_TBMR_CAP + Capture mode + 0x3 + + + + + TIMER_TBMR_TBCMR + GPTM Timer B Capture Mode + [2:2] + + + TIMER_TBMR_TBAMS + GPTM Timer B Alternate Mode Select + [3:3] + + + + + CTL + GPTM Control + 0x0000000C + + + TIMER_CTL_TAEN + GPTM Timer A Enable + [0:0] + + + TIMER_CTL_TASTALL + GPTM Timer A Stall Enable + [1:1] + + + TIMER_CTL_TAEVENT + GPTM Timer A Event Mode + [3:2] + + + TIMER_CTL_TAEVENT_POS + Positive edge + 0x0 + + + TIMER_CTL_TAEVENT_NEG + Negative edge + 0x1 + + + TIMER_CTL_TAEVENT_BOTH + Both edges + 0x3 + + + + + TIMER_CTL_RTCEN + GPTM RTC Enable + [4:4] + + + TIMER_CTL_TAOTE + GPTM Timer A Output Trigger Enable + [5:5] + + + TIMER_CTL_TAPWML + GPTM Timer A PWM Output Level + [6:6] + + + TIMER_CTL_TBEN + GPTM Timer B Enable + [8:8] + + + TIMER_CTL_TBSTALL + GPTM Timer B Stall Enable + [9:9] + + + TIMER_CTL_TBEVENT + GPTM Timer B Event Mode + [11:10] + + + TIMER_CTL_TBEVENT_POS + Positive edge + 0x0 + + + TIMER_CTL_TBEVENT_NEG + Negative edge + 0x1 + + + TIMER_CTL_TBEVENT_BOTH + Both edges + 0x3 + + + + + TIMER_CTL_TBOTE + GPTM Timer B Output Trigger Enable + [13:13] + + + TIMER_CTL_TBPWML + GPTM Timer B PWM Output Level + [14:14] + + + + + IMR + GPTM Interrupt Mask + 0x00000018 + + + TIMER_IMR_TATOIM + GPTM Timer A Time-Out Interrupt Mask + [0:0] + + + TIMER_IMR_CAMIM + GPTM Capture A Match Interrupt Mask + [1:1] + + + TIMER_IMR_CAEIM + GPTM Capture A Event Interrupt Mask + [2:2] + + + TIMER_IMR_RTCIM + GPTM RTC Interrupt Mask + [3:3] + + + TIMER_IMR_TBTOIM + GPTM Timer B Time-Out Interrupt Mask + [8:8] + + + TIMER_IMR_CBMIM + GPTM Capture B Match Interrupt Mask + [9:9] + + + TIMER_IMR_CBEIM + GPTM Capture B Event Interrupt Mask + [10:10] + + + + + RIS + GPTM Raw Interrupt Status + 0x0000001C + + + TIMER_RIS_TATORIS + GPTM Timer A Time-Out Raw Interrupt + [0:0] + + + TIMER_RIS_CAMRIS + GPTM Capture A Match Raw Interrupt + [1:1] + + + TIMER_RIS_CAERIS + GPTM Capture A Event Raw Interrupt + [2:2] + + + TIMER_RIS_RTCRIS + GPTM RTC Raw Interrupt + [3:3] + + + TIMER_RIS_TBTORIS + GPTM Timer B Time-Out Raw Interrupt + [8:8] + + + TIMER_RIS_CBMRIS + GPTM Capture B Match Raw Interrupt + [9:9] + + + TIMER_RIS_CBERIS + GPTM Capture B Event Raw Interrupt + [10:10] + + + + + MIS + GPTM Masked Interrupt Status + 0x00000020 + + + TIMER_MIS_TATOMIS + GPTM Timer A Time-Out Masked Interrupt + [0:0] + + + TIMER_MIS_CAMMIS + GPTM Capture A Match Masked Interrupt + [1:1] + + + TIMER_MIS_CAEMIS + GPTM Capture A Event Masked Interrupt + [2:2] + + + TIMER_MIS_RTCMIS + GPTM RTC Masked Interrupt + [3:3] + + + TIMER_MIS_TBTOMIS + GPTM Timer B Time-Out Masked Interrupt + [8:8] + + + TIMER_MIS_CBMMIS + GPTM Capture B Match Masked Interrupt + [9:9] + + + TIMER_MIS_CBEMIS + GPTM Capture B Event Masked Interrupt + [10:10] + + + + + ICR + GPTM Interrupt Clear + 0x00000024 + write-only + + + TIMER_ICR_TATOCINT + GPTM Timer A Time-Out Raw Interrupt + [0:0] + write-only + + + TIMER_ICR_CAMCINT + GPTM Capture A Match Interrupt Clear + [1:1] + write-only + + + TIMER_ICR_CAECINT + GPTM Capture A Event Interrupt Clear + [2:2] + write-only + + + TIMER_ICR_RTCCINT + GPTM RTC Interrupt Clear + [3:3] + write-only + + + TIMER_ICR_TBTOCINT + GPTM Timer B Time-Out Interrupt Clear + [8:8] + write-only + + + TIMER_ICR_CBMCINT + GPTM Capture B Match Interrupt Clear + [9:9] + write-only + + + TIMER_ICR_CBECINT + GPTM Capture B Event Interrupt Clear + [10:10] + write-only + + + + + TAILR + GPTM Timer A Interval Load + 0x00000028 + + + TIMER_TAILR_TAILRL + GPTM Timer A Interval Load Register Low + [15:0] + + + TIMER_TAILR_TAILRH + GPTM Timer A Interval Load Register High + [31:16] + + + + + TBILR + GPTM Timer B Interval Load + 0x0000002C + + + TIMER_TBILR_TBILRL + GPTM Timer B Interval Load Register + [15:0] + + + + + TAMATCHR + GPTM Timer A Match + 0x00000030 + + + TIMER_TAMATCHR_TAMRL + GPTM Timer A Match Register Low + [15:0] + + + TIMER_TAMATCHR_TAMRH + GPTM Timer A Match Register High + [31:16] + + + + + TBMATCHR + GPTM Timer B Match + 0x00000034 + + + TIMER_TBMATCHR_TBMRL + GPTM Timer B Match Register Low + [15:0] + + + + + TAPR + GPTM Timer A Prescale + 0x00000038 + + + TIMER_TAPR_TAPSR + GPTM Timer A Prescale + [7:0] + + + + + TBPR + GPTM Timer B Prescale + 0x0000003C + + + TIMER_TBPR_TBPSR + GPTM Timer B Prescale + [7:0] + + + + + TAPMR + GPTM TimerA Prescale Match + 0x00000040 + + + TIMER_TAPMR_TAPSMR + GPTM TimerA Prescale Match + [7:0] + + + + + TBPMR + GPTM TimerB Prescale Match + 0x00000044 + + + TIMER_TBPMR_TBPSMR + GPTM TimerB Prescale Match + [7:0] + + + + + TAR + GPTM Timer A + 0x00000048 + + + TIMER_TAR_TARL + GPTM Timer A Register Low + [15:0] + + + TIMER_TAR_TARH + GPTM Timer A Register High + [31:16] + + + + + TBR + GPTM Timer B + 0x0000004C + + + TIMER_TBR_TBRL + GPTM Timer B + [15:0] + + + + + + + TIMER1 + TIMER1 + 0x40031000 + + + TIMER2 + TIMER2 + 0x40032000 + + + ADC0 + Register map for ADC0 peripheral + ADC + ADC0 + 0x40038000 + + 0 + 0x00001000 + registers + + + + ACTSS + ADC Active Sample Sequencer + 0x00000000 + + + ADC_ACTSS_ASEN0 + ADC SS0 Enable + [0:0] + + + ADC_ACTSS_ASEN1 + ADC SS1 Enable + [1:1] + + + ADC_ACTSS_ASEN2 + ADC SS2 Enable + [2:2] + + + ADC_ACTSS_ASEN3 + ADC SS3 Enable + [3:3] + + + + + RIS + ADC Raw Interrupt Status + 0x00000004 + + + ADC_RIS_INR0 + SS0 Raw Interrupt Status + [0:0] + + + ADC_RIS_INR1 + SS1 Raw Interrupt Status + [1:1] + + + ADC_RIS_INR2 + SS2 Raw Interrupt Status + [2:2] + + + ADC_RIS_INR3 + SS3 Raw Interrupt Status + [3:3] + + + + + IM + ADC Interrupt Mask + 0x00000008 + + + ADC_IM_MASK0 + SS0 Interrupt Mask + [0:0] + + + ADC_IM_MASK1 + SS1 Interrupt Mask + [1:1] + + + ADC_IM_MASK2 + SS2 Interrupt Mask + [2:2] + + + ADC_IM_MASK3 + SS3 Interrupt Mask + [3:3] + + + + + ISC + ADC Interrupt Status and Clear + 0x0000000C + + + ADC_ISC_IN0 + SS0 Interrupt Status and Clear + [0:0] + + + ADC_ISC_IN1 + SS1 Interrupt Status and Clear + [1:1] + + + ADC_ISC_IN2 + SS2 Interrupt Status and Clear + [2:2] + + + ADC_ISC_IN3 + SS3 Interrupt Status and Clear + [3:3] + + + + + OSTAT + ADC Overflow Status + 0x00000010 + + + ADC_OSTAT_OV0 + SS0 FIFO Overflow + [0:0] + + + ADC_OSTAT_OV1 + SS1 FIFO Overflow + [1:1] + + + ADC_OSTAT_OV2 + SS2 FIFO Overflow + [2:2] + + + ADC_OSTAT_OV3 + SS3 FIFO Overflow + [3:3] + + + + + EMUX + ADC Event Multiplexer Select + 0x00000014 + + + ADC_EMUX_EM0 + SS0 Trigger Select + [3:0] + + + ADC_EMUX_EM0_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM0_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM0_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM0_TIMER + Timer + 0x5 + + + ADC_EMUX_EM0_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM0_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM0_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM0_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM1 + SS1 Trigger Select + [7:4] + + + ADC_EMUX_EM1_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM1_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM1_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM1_TIMER + Timer + 0x5 + + + ADC_EMUX_EM1_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM1_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM1_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM1_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM2 + SS2 Trigger Select + [11:8] + + + ADC_EMUX_EM2_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM2_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM2_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM2_TIMER + Timer + 0x5 + + + ADC_EMUX_EM2_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM2_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM2_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM2_ALWAYS + Always (continuously sample) + 0xf + + + + + ADC_EMUX_EM3 + SS3 Trigger Select + [15:12] + + + ADC_EMUX_EM3_PROCESSOR + Processor (default) + 0x0 + + + ADC_EMUX_EM3_COMP0 + Analog Comparator 0 + 0x1 + + + ADC_EMUX_EM3_EXTERNAL + External (GPIO PB4) + 0x4 + + + ADC_EMUX_EM3_TIMER + Timer + 0x5 + + + ADC_EMUX_EM3_PWM0 + PWM0 + 0x6 + + + ADC_EMUX_EM3_PWM1 + PWM1 + 0x7 + + + ADC_EMUX_EM3_PWM2 + PWM2 + 0x8 + + + ADC_EMUX_EM3_ALWAYS + Always (continuously sample) + 0xf + + + + + + + USTAT + ADC Underflow Status + 0x00000018 + + + ADC_USTAT_UV0 + SS0 FIFO Underflow + [0:0] + + + ADC_USTAT_UV1 + SS1 FIFO Underflow + [1:1] + + + ADC_USTAT_UV2 + SS2 FIFO Underflow + [2:2] + + + ADC_USTAT_UV3 + SS3 FIFO Underflow + [3:3] + + + + + SSPRI + ADC Sample Sequencer Priority + 0x00000020 + + + ADC_SSPRI_SS0 + SS0 Priority + [1:0] + + + ADC_SSPRI_SS0_1ST + First priority + 0x0 + + + ADC_SSPRI_SS0_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS0_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS0_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS1 + SS1 Priority + [5:4] + + + ADC_SSPRI_SS1_1ST + First priority + 0x0 + + + ADC_SSPRI_SS1_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS1_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS1_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS2 + SS2 Priority + [9:8] + + + ADC_SSPRI_SS2_1ST + First priority + 0x0 + + + ADC_SSPRI_SS2_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS2_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS2_4TH + Fourth priority + 0x3 + + + + + ADC_SSPRI_SS3 + SS3 Priority + [13:12] + + + ADC_SSPRI_SS3_1ST + First priority + 0x0 + + + ADC_SSPRI_SS3_2ND + Second priority + 0x1 + + + ADC_SSPRI_SS3_3RD + Third priority + 0x2 + + + ADC_SSPRI_SS3_4TH + Fourth priority + 0x3 + + + + + + + PSSI + ADC Processor Sample Sequence Initiate + 0x00000028 + + + ADC_PSSI_SS0 + SS0 Initiate + [0:0] + + + ADC_PSSI_SS1 + SS1 Initiate + [1:1] + + + ADC_PSSI_SS2 + SS2 Initiate + [2:2] + + + ADC_PSSI_SS3 + SS3 Initiate + [3:3] + + + + + SAC + ADC Sample Averaging Control + 0x00000030 + + + ADC_SAC_AVG + Hardware Averaging Control + [2:0] + + + ADC_SAC_AVG_OFF + No hardware oversampling + 0x0 + + + ADC_SAC_AVG_2X + 2x hardware oversampling + 0x1 + + + ADC_SAC_AVG_4X + 4x hardware oversampling + 0x2 + + + ADC_SAC_AVG_8X + 8x hardware oversampling + 0x3 + + + ADC_SAC_AVG_16X + 16x hardware oversampling + 0x4 + + + ADC_SAC_AVG_32X + 32x hardware oversampling + 0x5 + + + ADC_SAC_AVG_64X + 64x hardware oversampling + 0x6 + + + + + + + SSMUX0 + ADC Sample Sequence Input Multiplexer Select 0 + 0x00000040 + + + ADC_SSMUX0_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX0_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX0_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX0_MUX3 + 4th Sample Input Select + [13:12] + + + ADC_SSMUX0_MUX4 + 5th Sample Input Select + [17:16] + + + ADC_SSMUX0_MUX5 + 6th Sample Input Select + [21:20] + + + ADC_SSMUX0_MUX6 + 7th Sample Input Select + [25:24] + + + ADC_SSMUX0_MUX7 + 8th Sample Input Select + [29:28] + + + + + SSCTL0 + ADC Sample Sequence Control 0 + 0x00000044 + + + ADC_SSCTL0_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL0_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL0_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL0_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL0_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL0_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL0_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL0_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL0_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL0_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL0_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL0_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL0_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL0_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL0_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL0_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + ADC_SSCTL0_D4 + 5th Sample Diff Input Select + [16:16] + + + ADC_SSCTL0_END4 + 5th Sample is End of Sequence + [17:17] + + + ADC_SSCTL0_IE4 + 5th Sample Interrupt Enable + [18:18] + + + ADC_SSCTL0_TS4 + 5th Sample Temp Sensor Select + [19:19] + + + ADC_SSCTL0_D5 + 6th Sample Diff Input Select + [20:20] + + + ADC_SSCTL0_END5 + 6th Sample is End of Sequence + [21:21] + + + ADC_SSCTL0_IE5 + 6th Sample Interrupt Enable + [22:22] + + + ADC_SSCTL0_TS5 + 6th Sample Temp Sensor Select + [23:23] + + + ADC_SSCTL0_D6 + 7th Sample Diff Input Select + [24:24] + + + ADC_SSCTL0_END6 + 7th Sample is End of Sequence + [25:25] + + + ADC_SSCTL0_IE6 + 7th Sample Interrupt Enable + [26:26] + + + ADC_SSCTL0_TS6 + 7th Sample Temp Sensor Select + [27:27] + + + ADC_SSCTL0_D7 + 8th Sample Diff Input Select + [28:28] + + + ADC_SSCTL0_END7 + 8th Sample is End of Sequence + [29:29] + + + ADC_SSCTL0_IE7 + 8th Sample Interrupt Enable + [30:30] + + + ADC_SSCTL0_TS7 + 8th Sample Temp Sensor Select + [31:31] + + + + + SSFIFO0 + ADC Sample Sequence Result FIFO 0 + 0x00000048 + + + ADC_SSFIFO0_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT0 + ADC Sample Sequence FIFO 0 Status + 0x0000004C + + + ADC_SSFSTAT0_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT0_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT0_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT0_FULL + FIFO Full + [12:12] + + + + + SSMUX1 + ADC Sample Sequence Input Multiplexer Select 1 + 0x00000060 + + + ADC_SSMUX1_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX1_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX1_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX1_MUX3 + 4th Sample Input Select + [13:12] + + + + + SSCTL1 + ADC Sample Sequence Control 1 + 0x00000064 + + + ADC_SSCTL1_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL1_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL1_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL1_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL1_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL1_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL1_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL1_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL1_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL1_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL1_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL1_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL1_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL1_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL1_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL1_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + + + SSFIFO1 + ADC Sample Sequence Result FIFO 1 + 0x00000068 + + + ADC_SSFIFO1_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT1 + ADC Sample Sequence FIFO 1 Status + 0x0000006C + + + ADC_SSFSTAT1_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT1_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT1_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT1_FULL + FIFO Full + [12:12] + + + + + SSMUX2 + ADC Sample Sequence Input Multiplexer Select 2 + 0x00000080 + + + ADC_SSMUX2_MUX0 + 1st Sample Input Select + [1:0] + + + ADC_SSMUX2_MUX1 + 2nd Sample Input Select + [5:4] + + + ADC_SSMUX2_MUX2 + 3rd Sample Input Select + [9:8] + + + ADC_SSMUX2_MUX3 + 4th Sample Input Select + [13:12] + + + + + SSCTL2 + ADC Sample Sequence Control 2 + 0x00000084 + + + ADC_SSCTL2_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL2_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL2_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL2_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + ADC_SSCTL2_D1 + 2nd Sample Diff Input Select + [4:4] + + + ADC_SSCTL2_END1 + 2nd Sample is End of Sequence + [5:5] + + + ADC_SSCTL2_IE1 + 2nd Sample Interrupt Enable + [6:6] + + + ADC_SSCTL2_TS1 + 2nd Sample Temp Sensor Select + [7:7] + + + ADC_SSCTL2_D2 + 3rd Sample Diff Input Select + [8:8] + + + ADC_SSCTL2_END2 + 3rd Sample is End of Sequence + [9:9] + + + ADC_SSCTL2_IE2 + 3rd Sample Interrupt Enable + [10:10] + + + ADC_SSCTL2_TS2 + 3rd Sample Temp Sensor Select + [11:11] + + + ADC_SSCTL2_D3 + 4th Sample Diff Input Select + [12:12] + + + ADC_SSCTL2_END3 + 4th Sample is End of Sequence + [13:13] + + + ADC_SSCTL2_IE3 + 4th Sample Interrupt Enable + [14:14] + + + ADC_SSCTL2_TS3 + 4th Sample Temp Sensor Select + [15:15] + + + + + SSFIFO2 + ADC Sample Sequence Result FIFO 2 + 0x00000088 + + + ADC_SSFIFO2_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT2 + ADC Sample Sequence FIFO 2 Status + 0x0000008C + + + ADC_SSFSTAT2_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT2_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT2_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT2_FULL + FIFO Full + [12:12] + + + + + SSMUX3 + ADC Sample Sequence Input Multiplexer Select 3 + 0x000000A0 + + + ADC_SSMUX3_MUX0 + 1st Sample Input Select + [1:0] + + + + + SSCTL3 + ADC Sample Sequence Control 3 + 0x000000A4 + + + ADC_SSCTL3_D0 + 1st Sample Diff Input Select + [0:0] + + + ADC_SSCTL3_END0 + 1st Sample is End of Sequence + [1:1] + + + ADC_SSCTL3_IE0 + 1st Sample Interrupt Enable + [2:2] + + + ADC_SSCTL3_TS0 + 1st Sample Temp Sensor Select + [3:3] + + + + + SSFIFO3 + ADC Sample Sequence Result FIFO 3 + 0x000000A8 + + + ADC_SSFIFO3_DATA + Conversion Result Data + [9:0] + + + + + SSFSTAT3 + ADC Sample Sequence FIFO 3 Status + 0x000000AC + + + ADC_SSFSTAT3_TPTR + FIFO Tail Pointer + [3:0] + + + ADC_SSFSTAT3_HPTR + FIFO Head Pointer + [7:4] + + + ADC_SSFSTAT3_EMPTY + FIFO Empty + [8:8] + + + ADC_SSFSTAT3_FULL + FIFO Full + [12:12] + + + + + TMLB + ADC Test Mode Loopback + 0x00000100 + + + ADC_TMLB_LB + Loopback Mode Enable + [0:0] + + + + + + + COMP + Register map for COMP peripheral + COMP + COMP + 0x4003C000 + + 0 + 0x00001000 + registers + + + + ACMIS + Analog Comparator Masked Interrupt Status + 0x00000000 + + + COMP_ACMIS_IN0 + Comparator 0 Masked Interrupt Status + [0:0] + + + + + ACRIS + Analog Comparator Raw Interrupt Status + 0x00000004 + + + COMP_ACRIS_IN0 + Comparator 0 Interrupt Status + [0:0] + + + + + ACINTEN + Analog Comparator Interrupt Enable + 0x00000008 + + + COMP_ACINTEN_IN0 + Comparator 0 Interrupt Enable + [0:0] + + + + + ACREFCTL + Analog Comparator Reference Voltage Control + 0x00000010 + + + COMP_ACREFCTL_VREF + Resistor Ladder Voltage Ref + [3:0] + + + COMP_ACREFCTL_RNG + Resistor Ladder Range + [8:8] + + + COMP_ACREFCTL_EN + Resistor Ladder Enable + [9:9] + + + + + ACSTAT0 + Analog Comparator Status 0 + 0x00000020 + + + COMP_ACSTAT0_OVAL + Comparator Output Value + [1:1] + + + + + ACCTL0 + Analog Comparator Control 0 + 0x00000024 + + + COMP_ACCTL0_CINV + Comparator Output Invert + [1:1] + + + COMP_ACCTL0_ISEN + Interrupt Sense + [3:2] + + + COMP_ACCTL0_ISEN_LEVEL + Level sense, see ISLVAL + 0x0 + + + COMP_ACCTL0_ISEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL0_ISEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL0_ISEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL0_ISLVAL + Interrupt Sense Level Value + [4:4] + + + COMP_ACCTL0_TSEN + Trigger Sense + [6:5] + + + COMP_ACCTL0_TSEN_LEVEL + Level sense, see TSLVAL + 0x0 + + + COMP_ACCTL0_TSEN_FALL + Falling edge + 0x1 + + + COMP_ACCTL0_TSEN_RISE + Rising edge + 0x2 + + + COMP_ACCTL0_TSEN_BOTH + Either edge + 0x3 + + + + + COMP_ACCTL0_TSLVAL + Trigger Sense Level Value + [7:7] + + + COMP_ACCTL0_ASRCP + Analog Source Positive + [10:9] + + + COMP_ACCTL0_ASRCP_PIN + Pin value of Cn+ + 0x0 + + + COMP_ACCTL0_ASRCP_PIN0 + Pin value of C0+ + 0x1 + + + COMP_ACCTL0_ASRCP_REF + Internal voltage reference (VIREF) + 0x2 + + + + + COMP_ACCTL0_TOEN + Trigger Output Enable + [11:11] + + + + + + + FLASH_CTRL + Register map for FLASH_CTRL peripheral + FLASH_CTRL + FLASH_CTRL + 0x400FD000 + + 0 + 0x00001000 + registers + + + 0x1000 + 0x00001000 + registers + + + + FMA + Flash Memory Address + 0x00000000 + + + FLASH_FMA_OFFSET + Address Offset + [15:0] + + + + + FMD + Flash Memory Data + 0x00000004 + + + FLASH_FMD_DATA + Data Value + [31:0] + + + + + FMC + Flash Memory Control + 0x00000008 + + + FLASH_FMC_WRITE + Write a Word into Flash Memory + [0:0] + + + FLASH_FMC_ERASE + Erase a Page of Flash Memory + [1:1] + + + FLASH_FMC_MERASE + Mass Erase Flash Memory + [2:2] + + + FLASH_FMC_COMT + Commit Register Value + [3:3] + + + FLASH_FMC_WRKEY + FLASH write key + [31:17] + + + + + FCRIS + Flash Controller Raw Interrupt Status + 0x0000000C + + + FLASH_FCRIS_ARIS + Access Raw Interrupt Status + [0:0] + + + FLASH_FCRIS_PRIS + Programming Raw Interrupt Status + [1:1] + + + + + FCIM + Flash Controller Interrupt Mask + 0x00000010 + + + FLASH_FCIM_AMASK + Access Interrupt Mask + [0:0] + + + FLASH_FCIM_PMASK + Programming Interrupt Mask + [1:1] + + + + + FCMISC + Flash Controller Masked Interrupt Status and Clear + 0x00000014 + + + FLASH_FCMISC_AMISC + Access Masked Interrupt Status and Clear + [0:0] + + + FLASH_FCMISC_PMISC + Programming Masked Interrupt Status and Clear + [1:1] + + + + + FMPRE + Flash Memory Protection Read Enable + 0x00001130 + + + FMPPE + Flash Memory Protection Program Enable + 0x00001134 + + + USECRL + USec Reload + 0x00001140 + + + FLASH_USECRL + Microsecond Reload Value + [7:0] + + + + + + + SYSCTL + Register map for SYSCTL peripheral + SYSCTL + SYSCTL + 0x400FE000 + + 0 + 0x00001000 + registers + + + + DID0 + Device Identification 0 + 0x00000000 + + + SYSCTL_DID0_MIN + Minor Revision + [7:0] + + + SYSCTL_DID0_MIN_0 + Initial device, or a major revision update + 0x0 + + + SYSCTL_DID0_MIN_1 + First metal layer change + 0x1 + + + SYSCTL_DID0_MIN_2 + Second metal layer change + 0x2 + + + + + SYSCTL_DID0_MAJ + Major Revision + [15:8] + + + SYSCTL_DID0_MAJ_REVA + Revision A (initial device) + 0x0 + + + SYSCTL_DID0_MAJ_REVB + Revision B (first base layer revision) + 0x1 + + + SYSCTL_DID0_MAJ_REVC + Revision C (second base layer revision) + 0x2 + + + + + SYSCTL_DID0_VER + DID0 Version + [30:28] + + + SYSCTL_DID0_VER_0 + Initial DID0 register format definition for Stellaris(R) Sandstorm-class devices + 0x0 + + + + + + + DID1 + Device Identification 1 + 0x00000004 + + + SYSCTL_DID1_QUAL + Qualification Status + [1:0] + + + SYSCTL_DID1_QUAL_ES + Engineering Sample (unqualified) + 0x0 + + + SYSCTL_DID1_QUAL_PP + Pilot Production (unqualified) + 0x1 + + + SYSCTL_DID1_QUAL_FQ + Fully Qualified + 0x2 + + + + + SYSCTL_DID1_ROHS + RoHS-Compliance + [2:2] + + + SYSCTL_DID1_PKG + Package Type + [4:3] + + + SYSCTL_DID1_PKG_SOIC + SOIC package + 0x0 + + + SYSCTL_DID1_PKG_QFP + LQFP package + 0x1 + + + SYSCTL_DID1_PKG_QFN + QFN package + 0x3 + + + + + SYSCTL_DID1_TEMP + Temperature Range + [7:5] + + + SYSCTL_DID1_TEMP_C + Commercial temperature range (0C to 70C) + 0x0 + + + SYSCTL_DID1_TEMP_I + Industrial temperature range (-40C to 85C) + 0x1 + + + SYSCTL_DID1_TEMP_E + Extended temperature range (-40C to 105C) + 0x2 + + + + + SYSCTL_DID1_PRTNO + Part Number + [23:16] + + + SYSCTL_DID1_PRTNO_811 + LM3S811 + 0x32 + + + + + SYSCTL_DID1_FAM + Family + [27:24] + + + SYSCTL_DID1_FAM_STELLARIS + Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S + 0x0 + + + + + SYSCTL_DID1_VER + DID1 Version + [31:28] + + + SYSCTL_DID1_VER_0 + Initial DID1 register format definition, indicating a Stellaris LM3Snnn device + 0x0 + + + + + + + DC0 + Device Capabilities 0 + 0x00000008 + + + SYSCTL_DC0_FLASHSZ + Flash Size + [15:0] + + + SYSCTL_DC0_FLASHSZ_64KB + 64 KB of Flash + 0x1f + + + + + SYSCTL_DC0_SRAMSZ + SRAM Size + [31:16] + + + SYSCTL_DC0_SRAMSZ_8KB + 8 KB of SRAM + 0x1f + + + + + + + DC1 + Device Capabilities 1 + 0x00000010 + + + SYSCTL_DC1_JTAG + JTAG Present + [0:0] + + + SYSCTL_DC1_SWD + SWD Present + [1:1] + + + SYSCTL_DC1_SWO + SWO Trace Port Present + [2:2] + + + SYSCTL_DC1_WDT0 + Watchdog Timer 0 Present + [3:3] + + + SYSCTL_DC1_PLL + PLL Present + [4:4] + + + SYSCTL_DC1_TEMP + Temp Sensor Present + [5:5] + + + SYSCTL_DC1_MPU + MPU Present + [7:7] + + + SYSCTL_DC1_MINSYSDIV + System Clock Divider + [15:12] + + + SYSCTL_DC1_MINSYSDIV_50 + Specifies a 50-MHz CPU clock with a PLL divider of 4 + 0x3 + + + + + + + DC2 + Device Capabilities 2 + 0x00000014 + + + SYSCTL_DC2_UART0 + UART Module 0 Present + [0:0] + + + SYSCTL_DC2_UART1 + UART Module 1 Present + [1:1] + + + SYSCTL_DC2_SSI0 + SSI Module 0 Present + [4:4] + + + SYSCTL_DC2_I2C0 + I2C Module 0 Present + [12:12] + + + SYSCTL_DC2_TIMER0 + Timer Module 0 Present + [16:16] + + + SYSCTL_DC2_TIMER1 + Timer Module 1 Present + [17:17] + + + SYSCTL_DC2_TIMER2 + Timer Module 2 Present + [18:18] + + + SYSCTL_DC2_COMP0 + Analog Comparator 0 Present + [24:24] + + + + + DC3 + Device Capabilities 3 + 0x00000018 + + + SYSCTL_DC3_PWM0 + PWM0 Pin Present + [0:0] + + + SYSCTL_DC3_PWM1 + PWM1 Pin Present + [1:1] + + + SYSCTL_DC3_PWM2 + PWM2 Pin Present + [2:2] + + + SYSCTL_DC3_PWM3 + PWM3 Pin Present + [3:3] + + + SYSCTL_DC3_PWM4 + PWM4 Pin Present + [4:4] + + + SYSCTL_DC3_PWM5 + PWM5 Pin Present + [5:5] + + + SYSCTL_DC3_C0MINUS + C0- Pin Present + [6:6] + + + SYSCTL_DC3_C0PLUS + C0+ Pin Present + [7:7] + + + SYSCTL_DC3_C0O + C0o Pin Present + [8:8] + + + SYSCTL_DC3_CCP0 + CCP0 Pin Present + [24:24] + + + SYSCTL_DC3_CCP1 + CCP1 Pin Present + [25:25] + + + SYSCTL_DC3_CCP2 + CCP2 Pin Present + [26:26] + + + SYSCTL_DC3_CCP3 + CCP3 Pin Present + [27:27] + + + SYSCTL_DC3_CCP4 + CCP4 Pin Present + [28:28] + + + SYSCTL_DC3_CCP5 + CCP5 Pin Present + [29:29] + + + SYSCTL_DC3_32KHZ + 32KHz Input Clock Available + [31:31] + + + + + DC4 + Device Capabilities 4 + 0x0000001C + + + SYSCTL_DC4_GPIOA + GPIO Port A Present + [0:0] + + + SYSCTL_DC4_GPIOB + GPIO Port B Present + [1:1] + + + SYSCTL_DC4_GPIOC + GPIO Port C Present + [2:2] + + + SYSCTL_DC4_GPIOD + GPIO Port D Present + [3:3] + + + SYSCTL_DC4_GPIOE + GPIO Port E Present + [4:4] + + + + + PBORCTL + Brown-Out Reset Control + 0x00000030 + + + SYSCTL_PBORCTL_BORWT + BOR Wait and Check for Noise + [0:0] + + + SYSCTL_PBORCTL_BORIOR + BOR Interrupt or Reset + [1:1] + + + SYSCTL_PBORCTL_BORTIM + BOR Time Delay + [15:2] + + + + + LDOPCTL + LDO Power Control + 0x00000034 + + + SYSCTL_LDOPCTL + LDO Output Voltage + [5:0] + + + SYSCTL_LDOPCTL_2_50V + 2.50 + 0x0 + + + SYSCTL_LDOPCTL_2_45V + 2.45 + 0x1 + + + SYSCTL_LDOPCTL_2_40V + 2.40 + 0x2 + + + SYSCTL_LDOPCTL_2_35V + 2.35 + 0x3 + + + SYSCTL_LDOPCTL_2_30V + 2.30 + 0x4 + + + SYSCTL_LDOPCTL_2_25V + 2.25 + 0x5 + + + SYSCTL_LDOPCTL_2_75V + 2.75 + 0x1b + + + SYSCTL_LDOPCTL_2_70V + 2.70 + 0x1c + + + SYSCTL_LDOPCTL_2_65V + 2.65 + 0x1d + + + SYSCTL_LDOPCTL_2_60V + 2.60 + 0x1e + + + SYSCTL_LDOPCTL_2_55V + 2.55 + 0x1f + + + + + + + SRCR0 + Software Reset Control 0 + 0x00000040 + + + SRCR1 + Software Reset Control 1 + 0x00000044 + + + SYSCTL_SRCR1_UART0 + UART0 Reset Control + [0:0] + + + SYSCTL_SRCR1_UART1 + UART1 Reset Control + [1:1] + + + SYSCTL_SRCR1_SSI0 + SSI0 Reset Control + [4:4] + + + SYSCTL_SRCR1_I2C0 + I2C0 Reset Control + [12:12] + + + SYSCTL_SRCR1_TIMER0 + Timer 0 Reset Control + [16:16] + + + SYSCTL_SRCR1_TIMER1 + Timer 1 Reset Control + [17:17] + + + SYSCTL_SRCR1_TIMER2 + Timer 2 Reset Control + [18:18] + + + SYSCTL_SRCR1_COMP0 + Analog Comp 0 Reset Control + [24:24] + + + + + SRCR2 + Software Reset Control 2 + 0x00000048 + + + SYSCTL_SRCR2_GPIOA + Port A Reset Control + [0:0] + + + SYSCTL_SRCR2_GPIOB + Port B Reset Control + [1:1] + + + SYSCTL_SRCR2_GPIOC + Port C Reset Control + [2:2] + + + SYSCTL_SRCR2_GPIOD + Port D Reset Control + [3:3] + + + SYSCTL_SRCR2_GPIOE + Port E Reset Control + [4:4] + + + + + RIS + Raw Interrupt Status + 0x00000050 + + + SYSCTL_RIS_PLLFRIS + PLL Fault Raw Interrupt Status + [0:0] + + + SYSCTL_RIS_BORRIS + Brown-Out Reset Raw Interrupt Status + [1:1] + + + SYSCTL_RIS_LDORIS + LDO Power Unregulated Raw Interrupt Status + [2:2] + + + SYSCTL_RIS_MOFRIS + Main Oscillator Fault Raw Interrupt Status + [3:3] + + + SYSCTL_RIS_IOFRIS + Internal Oscillator Fault Raw Interrupt Status + [4:4] + + + SYSCTL_RIS_CLRIS + Current Limit Raw Interrupt Status + [5:5] + + + SYSCTL_RIS_PLLLRIS + PLL Lock Raw Interrupt Status + [6:6] + + + + + IMC + Interrupt Mask Control + 0x00000054 + + + SYSCTL_IMC_PLLFIM + PLL Fault Interrupt Mask + [0:0] + + + SYSCTL_IMC_BORIM + Brown-Out Reset Interrupt Mask + [1:1] + + + SYSCTL_IMC_LDOIM + LDO Power Unregulated Interrupt Mask + [2:2] + + + SYSCTL_IMC_MOFIM + Main Oscillator Fault Interrupt Mask + [3:3] + + + SYSCTL_IMC_IOFIM + Internal Oscillator Fault Interrupt Mask + [4:4] + + + SYSCTL_IMC_CLIM + Current Limit Interrupt Mask + [5:5] + + + SYSCTL_IMC_PLLLIM + PLL Lock Interrupt Mask + [6:6] + + + + + MISC + Masked Interrupt Status and Clear + 0x00000058 + + + SYSCTL_MISC_BORMIS + BOR Masked Interrupt Status + [1:1] + + + SYSCTL_MISC_LDOMIS + LDO Power Unregulated Masked Interrupt Status + [2:2] + + + SYSCTL_MISC_MOFMIS + Main Oscillator Fault Masked Interrupt Status + [3:3] + + + SYSCTL_MISC_IOFMIS + Internal Oscillator Fault Masked Interrupt Status + [4:4] + + + SYSCTL_MISC_CLMIS + Current Limit Masked Interrupt Status + [5:5] + + + SYSCTL_MISC_PLLLMIS + PLL Lock Masked Interrupt Status + [6:6] + + + + + RESC + Reset Cause + 0x0000005C + + + SYSCTL_RESC_EXT + External Reset + [0:0] + + + SYSCTL_RESC_POR + Power-On Reset + [1:1] + + + SYSCTL_RESC_BOR + Brown-Out Reset + [2:2] + + + SYSCTL_RESC_SW + Software Reset + [4:4] + + + SYSCTL_RESC_LDO + LDO Reset + [5:5] + + + + + RCC + Run-Mode Clock Configuration + 0x00000060 + + + SYSCTL_RCC_MOSCDIS + Main Oscillator Disable + [0:0] + + + SYSCTL_RCC_IOSCDIS + Internal Oscillator Disable + [1:1] + + + SYSCTL_RCC_MOSCVER + Main Oscillator Verification Timer + [2:2] + + + SYSCTL_RCC_IOSCVER + Internal Oscillator Verification Timer + [3:3] + + + SYSCTL_RCC_OSCSRC + Oscillator Source + [5:4] + + + SYSCTL_RCC_OSCSRC_MAIN + MOSC + 0x0 + + + SYSCTL_RCC_OSCSRC_INT + IOSC + 0x1 + + + SYSCTL_RCC_OSCSRC_INT4 + IOSC/4 + 0x2 + + + + + SYSCTL_RCC_XTAL + Crystal Value + [9:6] + + + SYSCTL_RCC_XTAL_1MHZ + 1 MHz + 0x0 + + + SYSCTL_RCC_XTAL_1_84MHZ + 1.8432 MHz + 0x1 + + + SYSCTL_RCC_XTAL_2MHZ + 2 MHz + 0x2 + + + SYSCTL_RCC_XTAL_2_45MHZ + 2.4576 MHz + 0x3 + + + SYSCTL_RCC_XTAL_3_57MHZ + 3.579545 MHz + 0x4 + + + SYSCTL_RCC_XTAL_3_68MHZ + 3.6864 MHz + 0x5 + + + SYSCTL_RCC_XTAL_4MHZ + 4 MHz + 0x6 + + + SYSCTL_RCC_XTAL_4_09MHZ + 4.096 MHz + 0x7 + + + SYSCTL_RCC_XTAL_4_91MHZ + 4.9152 MHz + 0x8 + + + SYSCTL_RCC_XTAL_5MHZ + 5 MHz + 0x9 + + + SYSCTL_RCC_XTAL_5_12MHZ + 5.12 MHz + 0xa + + + SYSCTL_RCC_XTAL_6MHZ + 6 MHz + 0xb + + + SYSCTL_RCC_XTAL_6_14MHZ + 6.144 MHz + 0xc + + + SYSCTL_RCC_XTAL_7_37MHZ + 7.3728 MHz + 0xd + + + SYSCTL_RCC_XTAL_8MHZ + 8 MHz + 0xe + + + SYSCTL_RCC_XTAL_8_19MHZ + 8.192 MHz + 0xf + + + + + SYSCTL_RCC_PLLVER + PLL Verification + [10:10] + + + SYSCTL_RCC_BYPASS + PLL Bypass + [11:11] + + + SYSCTL_RCC_OEN + PLL Output Enable + [12:12] + + + SYSCTL_RCC_PWRDN + PLL Power Down + [13:13] + + + SYSCTL_RCC_PWMDIV + PWM Unit Clock Divisor + [19:17] + + + SYSCTL_RCC_PWMDIV_2 + PWM clock /2 + 0x0 + + + SYSCTL_RCC_PWMDIV_4 + PWM clock /4 + 0x1 + + + SYSCTL_RCC_PWMDIV_8 + PWM clock /8 + 0x2 + + + SYSCTL_RCC_PWMDIV_16 + PWM clock /16 + 0x3 + + + SYSCTL_RCC_PWMDIV_32 + PWM clock /32 + 0x4 + + + SYSCTL_RCC_PWMDIV_64 + PWM clock /64 + 0x5 + + + + + SYSCTL_RCC_USEPWMDIV + Enable PWM Clock Divisor + [20:20] + + + SYSCTL_RCC_USESYSDIV + Enable System Clock Divider + [22:22] + + + SYSCTL_RCC_SYSDIV + System Clock Divisor + [26:23] + + + SYSCTL_RCC_SYSDIV_2 + System clock /2 + 0x1 + + + SYSCTL_RCC_SYSDIV_3 + System clock /3 + 0x2 + + + SYSCTL_RCC_SYSDIV_4 + System clock /4 + 0x3 + + + SYSCTL_RCC_SYSDIV_5 + System clock /5 + 0x4 + + + SYSCTL_RCC_SYSDIV_6 + System clock /6 + 0x5 + + + SYSCTL_RCC_SYSDIV_7 + System clock /7 + 0x6 + + + SYSCTL_RCC_SYSDIV_8 + System clock /8 + 0x7 + + + SYSCTL_RCC_SYSDIV_9 + System clock /9 + 0x8 + + + SYSCTL_RCC_SYSDIV_10 + System clock /10 + 0x9 + + + SYSCTL_RCC_SYSDIV_11 + System clock /11 + 0xa + + + SYSCTL_RCC_SYSDIV_12 + System clock /12 + 0xb + + + SYSCTL_RCC_SYSDIV_13 + System clock /13 + 0xc + + + SYSCTL_RCC_SYSDIV_14 + System clock /14 + 0xd + + + SYSCTL_RCC_SYSDIV_15 + System clock /15 + 0xe + + + SYSCTL_RCC_SYSDIV_16 + System clock /16 + 0xf + + + + + SYSCTL_RCC_ACG + Auto Clock Gating + [27:27] + + + + + PLLCFG + XTAL to PLL Translation + 0x00000064 + + + SYSCTL_PLLCFG_R + PLL R Value + [4:0] + + + SYSCTL_PLLCFG_F + PLL F Value + [13:5] + + + SYSCTL_PLLCFG_OD + PLL OD Value + [15:14] + + + SYSCTL_PLLCFG_OD_1 + Divide by 1 + 0x0 + + + SYSCTL_PLLCFG_OD_2 + Divide by 2 + 0x1 + + + SYSCTL_PLLCFG_OD_4 + Divide by 4 + 0x2 + + + + + + + RCGC0 + Run Mode Clock Gating Control Register 0 + 0x00000100 + + + SYSCTL_RCGC0_ADCSPD + ADC Sample Speed + [9:8] + + + SYSCTL_RCGC0_ADCSPD125K + 125K samples/second + 0x0 + + + SYSCTL_RCGC0_ADCSPD250K + 250K samples/second + 0x1 + + + SYSCTL_RCGC0_ADCSPD500K + 500K samples/second + 0x2 + + + + + + + RCGC1 + Run Mode Clock Gating Control Register 1 + 0x00000104 + + + SYSCTL_RCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_RCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_RCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_RCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_RCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_RCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_RCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_RCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + + + RCGC2 + Run Mode Clock Gating Control Register 2 + 0x00000108 + + + SYSCTL_RCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_RCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_RCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_RCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_RCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + + + SCGC0 + Sleep Mode Clock Gating Control Register 0 + 0x00000110 + + + SYSCTL_SCGC0_ADCSPD + ADC Sample Speed + [9:8] + + + SYSCTL_SCGC0_ADCSPD125K + 125K samples/second + 0x0 + + + SYSCTL_SCGC0_ADCSPD250K + 250K samples/second + 0x1 + + + SYSCTL_SCGC0_ADCSPD500K + 500K samples/second + 0x2 + + + + + + + SCGC1 + Sleep Mode Clock Gating Control Register 1 + 0x00000114 + + + SYSCTL_SCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_SCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_SCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_SCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_SCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_SCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_SCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_SCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + + + SCGC2 + Sleep Mode Clock Gating Control Register 2 + 0x00000118 + + + SYSCTL_SCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_SCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_SCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_SCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_SCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + + + DCGC0 + Deep Sleep Mode Clock Gating Control Register 0 + 0x00000120 + + + DCGC1 + Deep-Sleep Mode Clock Gating Control Register 1 + 0x00000124 + + + SYSCTL_DCGC1_UART0 + UART0 Clock Gating Control + [0:0] + + + SYSCTL_DCGC1_UART1 + UART1 Clock Gating Control + [1:1] + + + SYSCTL_DCGC1_SSI0 + SSI0 Clock Gating Control + [4:4] + + + SYSCTL_DCGC1_I2C0 + I2C0 Clock Gating Control + [12:12] + + + SYSCTL_DCGC1_TIMER0 + Timer 0 Clock Gating Control + [16:16] + + + SYSCTL_DCGC1_TIMER1 + Timer 1 Clock Gating Control + [17:17] + + + SYSCTL_DCGC1_TIMER2 + Timer 2 Clock Gating Control + [18:18] + + + SYSCTL_DCGC1_COMP0 + Analog Comparator 0 Clock Gating + [24:24] + + + + + DCGC2 + Deep Sleep Mode Clock Gating Control Register 2 + 0x00000128 + + + SYSCTL_DCGC2_GPIOA + Port A Clock Gating Control + [0:0] + + + SYSCTL_DCGC2_GPIOB + Port B Clock Gating Control + [1:1] + + + SYSCTL_DCGC2_GPIOC + Port C Clock Gating Control + [2:2] + + + SYSCTL_DCGC2_GPIOD + Port D Clock Gating Control + [3:3] + + + SYSCTL_DCGC2_GPIOE + Port E Clock Gating Control + [4:4] + + + + + DSLPCLKCFG + Deep Sleep Clock Configuration + 0x00000144 + + + SYSCTL_DSLPCLKCFG_IOSC + IOSC Clock Source + [0:0] + + + + + CLKVCLR + Clock Verification Clear + 0x00000150 + + + SYSCTL_CLKVCLR_VERCLR + Clock Verification Clear + [0:0] + + + + + LDOARST + Allow Unregulated LDO to Reset the Part + 0x00000160 + + + SYSCTL_LDOARST_LDOARST + LDO Reset + [0:0] + + + + + + + NVIC + Register map for NVIC peripheral + NVIC + NVIC + 0xE000E000 + + 0 + 0x00001000 + registers + + + + INT_TYPE + Interrupt Controller Type Reg + 0x00000004 + + + NVIC_INT_TYPE_LINES + Number of interrupt lines (x32) + [4:0] + + + + + ST_CTRL + SysTick Control and Status Register + 0x00000010 + + + NVIC_ST_CTRL_ENABLE + Enable + [0:0] + + + NVIC_ST_CTRL_INTEN + Interrupt Enable + [1:1] + + + NVIC_ST_CTRL_CLK_SRC + Clock Source + [2:2] + + + NVIC_ST_CTRL_COUNT + Count Flag + [16:16] + + + + + ST_RELOAD + SysTick Reload Value Register + 0x00000014 + + + NVIC_ST_RELOAD + Reload Value + [23:0] + + + + + ST_CURRENT + SysTick Current Value Register + 0x00000018 + + + NVIC_ST_CURRENT + Current Value + [23:0] + + + + + ST_CAL + SysTick Calibration Value Reg + 0x0000001C + + + NVIC_ST_CAL_ONEMS + 1ms reference value + [23:0] + + + NVIC_ST_CAL_SKEW + Clock skew + [30:30] + + + NVIC_ST_CAL_NOREF + No reference clock + [31:31] + + + + + EN0 + Interrupt 0-31 Set Enable + 0x00000100 + + + NVIC_EN0_INT + Interrupt Enable + [29:0] + + + NVIC_EN0_INT0 + Interrupt 0 enable + 0x1 + + + NVIC_EN0_INT1 + Interrupt 1 enable + 0x2 + + + NVIC_EN0_INT2 + Interrupt 2 enable + 0x4 + + + NVIC_EN0_INT3 + Interrupt 3 enable + 0x8 + + + NVIC_EN0_INT4 + Interrupt 4 enable + 0x10 + + + NVIC_EN0_INT5 + Interrupt 5 enable + 0x20 + + + NVIC_EN0_INT6 + Interrupt 6 enable + 0x40 + + + NVIC_EN0_INT7 + Interrupt 7 enable + 0x80 + + + NVIC_EN0_INT8 + Interrupt 8 enable + 0x100 + + + NVIC_EN0_INT9 + Interrupt 9 enable + 0x200 + + + NVIC_EN0_INT10 + Interrupt 10 enable + 0x400 + + + NVIC_EN0_INT11 + Interrupt 11 enable + 0x800 + + + NVIC_EN0_INT12 + Interrupt 12 enable + 0x1000 + + + NVIC_EN0_INT13 + Interrupt 13 enable + 0x2000 + + + NVIC_EN0_INT14 + Interrupt 14 enable + 0x4000 + + + NVIC_EN0_INT15 + Interrupt 15 enable + 0x8000 + + + NVIC_EN0_INT16 + Interrupt 16 enable + 0x10000 + + + NVIC_EN0_INT17 + Interrupt 17 enable + 0x20000 + + + NVIC_EN0_INT18 + Interrupt 18 enable + 0x40000 + + + NVIC_EN0_INT19 + Interrupt 19 enable + 0x80000 + + + NVIC_EN0_INT20 + Interrupt 20 enable + 0x100000 + + + NVIC_EN0_INT21 + Interrupt 21 enable + 0x200000 + + + NVIC_EN0_INT22 + Interrupt 22 enable + 0x400000 + + + NVIC_EN0_INT23 + Interrupt 23 enable + 0x800000 + + + NVIC_EN0_INT24 + Interrupt 24 enable + 0x1000000 + + + NVIC_EN0_INT25 + Interrupt 25 enable + 0x2000000 + + + NVIC_EN0_INT26 + Interrupt 26 enable + 0x4000000 + + + NVIC_EN0_INT27 + Interrupt 27 enable + 0x8000000 + + + NVIC_EN0_INT28 + Interrupt 28 enable + 0x10000000 + + + NVIC_EN0_INT29 + Interrupt 29 enable + 0x20000000 + + + + + + + DIS0 + Interrupt 0-31 Clear Enable + 0x00000180 + + + NVIC_DIS0_INT + Interrupt Disable + [29:0] + + + NVIC_DIS0_INT0 + Interrupt 0 disable + 0x1 + + + NVIC_DIS0_INT1 + Interrupt 1 disable + 0x2 + + + NVIC_DIS0_INT2 + Interrupt 2 disable + 0x4 + + + NVIC_DIS0_INT3 + Interrupt 3 disable + 0x8 + + + NVIC_DIS0_INT4 + Interrupt 4 disable + 0x10 + + + NVIC_DIS0_INT5 + Interrupt 5 disable + 0x20 + + + NVIC_DIS0_INT6 + Interrupt 6 disable + 0x40 + + + NVIC_DIS0_INT7 + Interrupt 7 disable + 0x80 + + + NVIC_DIS0_INT8 + Interrupt 8 disable + 0x100 + + + NVIC_DIS0_INT9 + Interrupt 9 disable + 0x200 + + + NVIC_DIS0_INT10 + Interrupt 10 disable + 0x400 + + + NVIC_DIS0_INT11 + Interrupt 11 disable + 0x800 + + + NVIC_DIS0_INT12 + Interrupt 12 disable + 0x1000 + + + NVIC_DIS0_INT13 + Interrupt 13 disable + 0x2000 + + + NVIC_DIS0_INT14 + Interrupt 14 disable + 0x4000 + + + NVIC_DIS0_INT15 + Interrupt 15 disable + 0x8000 + + + NVIC_DIS0_INT16 + Interrupt 16 disable + 0x10000 + + + NVIC_DIS0_INT17 + Interrupt 17 disable + 0x20000 + + + NVIC_DIS0_INT18 + Interrupt 18 disable + 0x40000 + + + NVIC_DIS0_INT19 + Interrupt 19 disable + 0x80000 + + + NVIC_DIS0_INT20 + Interrupt 20 disable + 0x100000 + + + NVIC_DIS0_INT21 + Interrupt 21 disable + 0x200000 + + + NVIC_DIS0_INT22 + Interrupt 22 disable + 0x400000 + + + NVIC_DIS0_INT23 + Interrupt 23 disable + 0x800000 + + + NVIC_DIS0_INT24 + Interrupt 24 disable + 0x1000000 + + + NVIC_DIS0_INT25 + Interrupt 25 disable + 0x2000000 + + + NVIC_DIS0_INT26 + Interrupt 26 disable + 0x4000000 + + + NVIC_DIS0_INT27 + Interrupt 27 disable + 0x8000000 + + + NVIC_DIS0_INT28 + Interrupt 28 disable + 0x10000000 + + + NVIC_DIS0_INT29 + Interrupt 29 disable + 0x20000000 + + + + + + + PEND0 + Interrupt 0-31 Set Pending + 0x00000200 + + + NVIC_PEND0_INT + Interrupt Set Pending + [29:0] + + + NVIC_PEND0_INT0 + Interrupt 0 pend + 0x1 + + + NVIC_PEND0_INT1 + Interrupt 1 pend + 0x2 + + + NVIC_PEND0_INT2 + Interrupt 2 pend + 0x4 + + + NVIC_PEND0_INT3 + Interrupt 3 pend + 0x8 + + + NVIC_PEND0_INT4 + Interrupt 4 pend + 0x10 + + + NVIC_PEND0_INT5 + Interrupt 5 pend + 0x20 + + + NVIC_PEND0_INT6 + Interrupt 6 pend + 0x40 + + + NVIC_PEND0_INT7 + Interrupt 7 pend + 0x80 + + + NVIC_PEND0_INT8 + Interrupt 8 pend + 0x100 + + + NVIC_PEND0_INT9 + Interrupt 9 pend + 0x200 + + + NVIC_PEND0_INT10 + Interrupt 10 pend + 0x400 + + + NVIC_PEND0_INT11 + Interrupt 11 pend + 0x800 + + + NVIC_PEND0_INT12 + Interrupt 12 pend + 0x1000 + + + NVIC_PEND0_INT13 + Interrupt 13 pend + 0x2000 + + + NVIC_PEND0_INT14 + Interrupt 14 pend + 0x4000 + + + NVIC_PEND0_INT15 + Interrupt 15 pend + 0x8000 + + + NVIC_PEND0_INT16 + Interrupt 16 pend + 0x10000 + + + NVIC_PEND0_INT17 + Interrupt 17 pend + 0x20000 + + + NVIC_PEND0_INT18 + Interrupt 18 pend + 0x40000 + + + NVIC_PEND0_INT19 + Interrupt 19 pend + 0x80000 + + + NVIC_PEND0_INT20 + Interrupt 20 pend + 0x100000 + + + NVIC_PEND0_INT21 + Interrupt 21 pend + 0x200000 + + + NVIC_PEND0_INT22 + Interrupt 22 pend + 0x400000 + + + NVIC_PEND0_INT23 + Interrupt 23 pend + 0x800000 + + + NVIC_PEND0_INT24 + Interrupt 24 pend + 0x1000000 + + + NVIC_PEND0_INT25 + Interrupt 25 pend + 0x2000000 + + + NVIC_PEND0_INT26 + Interrupt 26 pend + 0x4000000 + + + NVIC_PEND0_INT27 + Interrupt 27 pend + 0x8000000 + + + NVIC_PEND0_INT28 + Interrupt 28 pend + 0x10000000 + + + NVIC_PEND0_INT29 + Interrupt 29 pend + 0x20000000 + + + + + + + UNPEND0 + Interrupt 0-31 Clear Pending + 0x00000280 + + + NVIC_UNPEND0_INT + Interrupt Clear Pending + [29:0] + + + NVIC_UNPEND0_INT0 + Interrupt 0 unpend + 0x1 + + + NVIC_UNPEND0_INT1 + Interrupt 1 unpend + 0x2 + + + NVIC_UNPEND0_INT2 + Interrupt 2 unpend + 0x4 + + + NVIC_UNPEND0_INT3 + Interrupt 3 unpend + 0x8 + + + NVIC_UNPEND0_INT4 + Interrupt 4 unpend + 0x10 + + + NVIC_UNPEND0_INT5 + Interrupt 5 unpend + 0x20 + + + NVIC_UNPEND0_INT6 + Interrupt 6 unpend + 0x40 + + + NVIC_UNPEND0_INT7 + Interrupt 7 unpend + 0x80 + + + NVIC_UNPEND0_INT8 + Interrupt 8 unpend + 0x100 + + + NVIC_UNPEND0_INT9 + Interrupt 9 unpend + 0x200 + + + NVIC_UNPEND0_INT10 + Interrupt 10 unpend + 0x400 + + + NVIC_UNPEND0_INT11 + Interrupt 11 unpend + 0x800 + + + NVIC_UNPEND0_INT12 + Interrupt 12 unpend + 0x1000 + + + NVIC_UNPEND0_INT13 + Interrupt 13 unpend + 0x2000 + + + NVIC_UNPEND0_INT14 + Interrupt 14 unpend + 0x4000 + + + NVIC_UNPEND0_INT15 + Interrupt 15 unpend + 0x8000 + + + NVIC_UNPEND0_INT16 + Interrupt 16 unpend + 0x10000 + + + NVIC_UNPEND0_INT17 + Interrupt 17 unpend + 0x20000 + + + NVIC_UNPEND0_INT18 + Interrupt 18 unpend + 0x40000 + + + NVIC_UNPEND0_INT19 + Interrupt 19 unpend + 0x80000 + + + NVIC_UNPEND0_INT20 + Interrupt 20 unpend + 0x100000 + + + NVIC_UNPEND0_INT21 + Interrupt 21 unpend + 0x200000 + + + NVIC_UNPEND0_INT22 + Interrupt 22 unpend + 0x400000 + + + NVIC_UNPEND0_INT23 + Interrupt 23 unpend + 0x800000 + + + NVIC_UNPEND0_INT24 + Interrupt 24 unpend + 0x1000000 + + + NVIC_UNPEND0_INT25 + Interrupt 25 unpend + 0x2000000 + + + NVIC_UNPEND0_INT26 + Interrupt 26 unpend + 0x4000000 + + + NVIC_UNPEND0_INT27 + Interrupt 27 unpend + 0x8000000 + + + NVIC_UNPEND0_INT28 + Interrupt 28 unpend + 0x10000000 + + + NVIC_UNPEND0_INT29 + Interrupt 29 unpend + 0x20000000 + + + + + + + ACTIVE0 + Interrupt 0-31 Active Bit + 0x00000300 + + + NVIC_ACTIVE0_INT + Interrupt Active + [29:0] + + + NVIC_ACTIVE0_INT0 + Interrupt 0 active + 0x1 + + + NVIC_ACTIVE0_INT1 + Interrupt 1 active + 0x2 + + + NVIC_ACTIVE0_INT2 + Interrupt 2 active + 0x4 + + + NVIC_ACTIVE0_INT3 + Interrupt 3 active + 0x8 + + + NVIC_ACTIVE0_INT4 + Interrupt 4 active + 0x10 + + + NVIC_ACTIVE0_INT5 + Interrupt 5 active + 0x20 + + + NVIC_ACTIVE0_INT6 + Interrupt 6 active + 0x40 + + + NVIC_ACTIVE0_INT7 + Interrupt 7 active + 0x80 + + + NVIC_ACTIVE0_INT8 + Interrupt 8 active + 0x100 + + + NVIC_ACTIVE0_INT9 + Interrupt 9 active + 0x200 + + + NVIC_ACTIVE0_INT10 + Interrupt 10 active + 0x400 + + + NVIC_ACTIVE0_INT11 + Interrupt 11 active + 0x800 + + + NVIC_ACTIVE0_INT12 + Interrupt 12 active + 0x1000 + + + NVIC_ACTIVE0_INT13 + Interrupt 13 active + 0x2000 + + + NVIC_ACTIVE0_INT14 + Interrupt 14 active + 0x4000 + + + NVIC_ACTIVE0_INT15 + Interrupt 15 active + 0x8000 + + + NVIC_ACTIVE0_INT16 + Interrupt 16 active + 0x10000 + + + NVIC_ACTIVE0_INT17 + Interrupt 17 active + 0x20000 + + + NVIC_ACTIVE0_INT18 + Interrupt 18 active + 0x40000 + + + NVIC_ACTIVE0_INT19 + Interrupt 19 active + 0x80000 + + + NVIC_ACTIVE0_INT20 + Interrupt 20 active + 0x100000 + + + NVIC_ACTIVE0_INT21 + Interrupt 21 active + 0x200000 + + + NVIC_ACTIVE0_INT22 + Interrupt 22 active + 0x400000 + + + NVIC_ACTIVE0_INT23 + Interrupt 23 active + 0x800000 + + + NVIC_ACTIVE0_INT24 + Interrupt 24 active + 0x1000000 + + + NVIC_ACTIVE0_INT25 + Interrupt 25 active + 0x2000000 + + + NVIC_ACTIVE0_INT26 + Interrupt 26 active + 0x4000000 + + + NVIC_ACTIVE0_INT27 + Interrupt 27 active + 0x8000000 + + + NVIC_ACTIVE0_INT28 + Interrupt 28 active + 0x10000000 + + + NVIC_ACTIVE0_INT29 + Interrupt 29 active + 0x20000000 + + + + + + + PRI0 + Interrupt 0-3 Priority + 0x00000400 + + + NVIC_PRI0_INT0 + Interrupt 0 Priority Mask + [7:5] + + + NVIC_PRI0_INT1 + Interrupt 1 Priority Mask + [15:13] + + + NVIC_PRI0_INT2 + Interrupt 2 Priority Mask + [23:21] + + + NVIC_PRI0_INT3 + Interrupt 3 Priority Mask + [31:29] + + + + + PRI1 + Interrupt 4-7 Priority + 0x00000404 + + + NVIC_PRI1_INT4 + Interrupt 4 Priority Mask + [7:5] + + + NVIC_PRI1_INT5 + Interrupt 5 Priority Mask + [15:13] + + + NVIC_PRI1_INT6 + Interrupt 6 Priority Mask + [23:21] + + + NVIC_PRI1_INT7 + Interrupt 7 Priority Mask + [31:29] + + + + + PRI2 + Interrupt 8-11 Priority + 0x00000408 + + + NVIC_PRI2_INT8 + Interrupt 8 Priority Mask + [7:5] + + + NVIC_PRI2_INT9 + Interrupt 9 Priority Mask + [15:13] + + + NVIC_PRI2_INT10 + Interrupt 10 Priority Mask + [23:21] + + + NVIC_PRI2_INT11 + Interrupt 11 Priority Mask + [31:29] + + + + + PRI3 + Interrupt 12-15 Priority + 0x0000040C + + + NVIC_PRI3_INT12 + Interrupt 12 Priority Mask + [7:5] + + + NVIC_PRI3_INT13 + Interrupt 13 Priority Mask + [15:13] + + + NVIC_PRI3_INT14 + Interrupt 14 Priority Mask + [23:21] + + + NVIC_PRI3_INT15 + Interrupt 15 Priority Mask + [31:29] + + + + + PRI4 + Interrupt 16-19 Priority + 0x00000410 + + + NVIC_PRI4_INT16 + Interrupt 16 Priority Mask + [7:5] + + + NVIC_PRI4_INT17 + Interrupt 17 Priority Mask + [15:13] + + + NVIC_PRI4_INT18 + Interrupt 18 Priority Mask + [23:21] + + + NVIC_PRI4_INT19 + Interrupt 19 Priority Mask + [31:29] + + + + + PRI5 + Interrupt 20-23 Priority + 0x00000414 + + + NVIC_PRI5_INT20 + Interrupt 20 Priority Mask + [7:5] + + + NVIC_PRI5_INT21 + Interrupt 21 Priority Mask + [15:13] + + + NVIC_PRI5_INT22 + Interrupt 22 Priority Mask + [23:21] + + + NVIC_PRI5_INT23 + Interrupt 23 Priority Mask + [31:29] + + + + + PRI6 + Interrupt 24-27 Priority + 0x00000418 + + + NVIC_PRI6_INT24 + Interrupt 24 Priority Mask + [7:5] + + + NVIC_PRI6_INT25 + Interrupt 25 Priority Mask + [15:13] + + + NVIC_PRI6_INT26 + Interrupt 26 Priority Mask + [23:21] + + + NVIC_PRI6_INT27 + Interrupt 27 Priority Mask + [31:29] + + + + + PRI7 + Interrupt 28-31 Priority + 0x0000041C + + + NVIC_PRI7_INT28 + Interrupt 28 Priority Mask + [7:5] + + + NVIC_PRI7_INT29 + Interrupt 29 Priority Mask + [15:13] + + + NVIC_PRI7_INT30 + Interrupt 30 Priority Mask + [23:21] + + + NVIC_PRI7_INT31 + Interrupt 31 Priority Mask + [31:29] + + + + + CPUID + CPU ID Base + 0x00000D00 + + + NVIC_CPUID_REV + Revision Number + [3:0] + + + NVIC_CPUID_PARTNO + Part Number + [15:4] + + + NVIC_CPUID_PARTNO_CM3 + Cortex-M3 processor + 0xc23 + + + + + NVIC_CPUID_CON + Constant + [19:16] + + + NVIC_CPUID_VAR + Variant Number + [23:20] + + + NVIC_CPUID_IMP + Implementer Code + [31:24] + + + NVIC_CPUID_IMP_ARM + ARM + 0x41 + + + + + + + INT_CTRL + Interrupt Control and State + 0x00000D04 + + + NVIC_INT_CTRL_VEC_ACT + Interrupt Pending Vector Number + [5:0] + + + NVIC_INT_CTRL_RET_BASE + Return to Base + [11:11] + + + NVIC_INT_CTRL_VEC_PEN + Interrupt Pending Vector Number + [17:12] + + + NVIC_INT_CTRL_VEC_PEN_NMI + NMI + 0x2 + + + NVIC_INT_CTRL_VEC_PEN_HARD + Hard fault + 0x3 + + + NVIC_INT_CTRL_VEC_PEN_MEM + Memory management fault + 0x4 + + + NVIC_INT_CTRL_VEC_PEN_BUS + Bus fault + 0x5 + + + NVIC_INT_CTRL_VEC_PEN_USG + Usage fault + 0x6 + + + NVIC_INT_CTRL_VEC_PEN_SVC + SVCall + 0xb + + + NVIC_INT_CTRL_VEC_PEN_PNDSV + PendSV + 0xe + + + NVIC_INT_CTRL_VEC_PEN_TICK + SysTick + 0xf + + + + + NVIC_INT_CTRL_ISR_PEND + Interrupt Pending + [22:22] + + + NVIC_INT_CTRL_ISR_PRE + Debug Interrupt Handling + [23:23] + + + NVIC_INT_CTRL_PENDSTCLR + SysTick Clear Pending + [25:25] + + + NVIC_INT_CTRL_PENDSTSET + SysTick Set Pending + [26:26] + + + NVIC_INT_CTRL_UNPEND_SV + PendSV Clear Pending + [27:27] + + + NVIC_INT_CTRL_PEND_SV + PendSV Set Pending + [28:28] + + + NVIC_INT_CTRL_NMI_SET + NMI Set Pending + [31:31] + + + + + VTABLE + Vector Table Offset + 0x00000D08 + + + NVIC_VTABLE_OFFSET + Vector Table Offset + [28:8] + + + NVIC_VTABLE_BASE + Vector Table Base + [29:29] + + + + + APINT + Application Interrupt and Reset Control + 0x00000D0C + + + NVIC_APINT_VECT_RESET + System Reset + [0:0] + + + NVIC_APINT_VECT_CLR_ACT + Clear Active NMI / Fault + [1:1] + + + NVIC_APINT_SYSRESETREQ + System Reset Request + [2:2] + + + NVIC_APINT_PRIGROUP + Interrupt Priority Grouping + [10:8] + + + NVIC_APINT_PRIGROUP_7_1 + Priority group 7.1 split + 0x0 + + + NVIC_APINT_PRIGROUP_6_2 + Priority group 6.2 split + 0x1 + + + NVIC_APINT_PRIGROUP_5_3 + Priority group 5.3 split + 0x2 + + + NVIC_APINT_PRIGROUP_4_4 + Priority group 4.4 split + 0x3 + + + NVIC_APINT_PRIGROUP_3_5 + Priority group 3.5 split + 0x4 + + + NVIC_APINT_PRIGROUP_2_6 + Priority group 2.6 split + 0x5 + + + NVIC_APINT_PRIGROUP_1_7 + Priority group 1.7 split + 0x6 + + + NVIC_APINT_PRIGROUP_0_8 + Priority group 0.8 split + 0x7 + + + + + NVIC_APINT_ENDIANESS + Data Endianess + [15:15] + + + NVIC_APINT_VECTKEY + Register Key + [31:16] + + + NVIC_APINT_VECTKEY + Vector key + 0x5fa + + + + + + + SYS_CTRL + System Control + 0x00000D10 + + + NVIC_SYS_CTRL_SLEEPEXIT + Sleep on ISR Exit + [1:1] + + + NVIC_SYS_CTRL_SLEEPDEEP + Deep Sleep Enable + [2:2] + + + NVIC_SYS_CTRL_SEVONPEND + Wake Up on Pending + [4:4] + + + + + CFG_CTRL + Configuration and Control + 0x00000D14 + + + NVIC_CFG_CTRL_BASE_THR + Thread State Control + [0:0] + + + NVIC_CFG_CTRL_MAIN_PEND + Allow Main Interrupt Trigger + [1:1] + + + NVIC_CFG_CTRL_UNALIGNED + Trap on Unaligned Access + [3:3] + + + NVIC_CFG_CTRL_DIV0 + Trap on Divide by 0 + [4:4] + + + NVIC_CFG_CTRL_BFHFNMIGN + Ignore Bus Fault in NMI and Fault + [8:8] + + + NVIC_CFG_CTRL_STKALIGN + Stack Alignment on Exception Entry + [9:9] + + + + + SYS_PRI1 + System Handler Priority 1 + 0x00000D18 + + + NVIC_SYS_PRI1_MEM + Memory Management Fault Priority + [7:5] + + + NVIC_SYS_PRI1_BUS + Bus Fault Priority + [15:13] + + + NVIC_SYS_PRI1_USAGE + Usage Fault Priority + [23:21] + + + + + SYS_PRI2 + System Handler Priority 2 + 0x00000D1C + + + NVIC_SYS_PRI2_SVC + SVCall Priority + [31:29] + + + + + SYS_PRI3 + System Handler Priority 3 + 0x00000D20 + + + NVIC_SYS_PRI3_DEBUG + Debug Priority + [7:5] + + + NVIC_SYS_PRI3_PENDSV + PendSV Priority + [23:21] + + + NVIC_SYS_PRI3_TICK + SysTick Exception Priority + [31:29] + + + + + SYS_HND_CTRL + System Handler Control and State + 0x00000D24 + + + NVIC_SYS_HND_CTRL_MEMA + Memory Management Fault Active + [0:0] + + + NVIC_SYS_HND_CTRL_BUSA + Bus Fault Active + [1:1] + + + NVIC_SYS_HND_CTRL_USGA + Usage Fault Active + [3:3] + + + NVIC_SYS_HND_CTRL_SVCA + SVC Call Active + [7:7] + + + NVIC_SYS_HND_CTRL_MON + Debug Monitor Active + [8:8] + + + NVIC_SYS_HND_CTRL_PNDSV + PendSV Exception Active + [10:10] + + + NVIC_SYS_HND_CTRL_TICK + SysTick Exception Active + [11:11] + + + NVIC_SYS_HND_CTRL_USAGEP + Usage Fault Pending + [12:12] + + + NVIC_SYS_HND_CTRL_MEMP + Memory Management Fault Pending + [13:13] + + + NVIC_SYS_HND_CTRL_BUSP + Bus Fault Pending + [14:14] + + + NVIC_SYS_HND_CTRL_SVC + SVC Call Pending + [15:15] + + + NVIC_SYS_HND_CTRL_MEM + Memory Management Fault Enable + [16:16] + + + NVIC_SYS_HND_CTRL_BUS + Bus Fault Enable + [17:17] + + + NVIC_SYS_HND_CTRL_USAGE + Usage Fault Enable + [18:18] + + + + + FAULT_STAT + Configurable Fault Status + 0x00000D28 + + + NVIC_FAULT_STAT_IERR + Instruction Access Violation + [0:0] + + + NVIC_FAULT_STAT_DERR + Data Access Violation + [1:1] + + + NVIC_FAULT_STAT_MUSTKE + Unstack Access Violation + [3:3] + + + NVIC_FAULT_STAT_MSTKE + Stack Access Violation + [4:4] + + + NVIC_FAULT_STAT_MMARV + Memory Management Fault Address Register Valid + [7:7] + + + NVIC_FAULT_STAT_IBUS + Instruction Bus Error + [8:8] + + + NVIC_FAULT_STAT_PRECISE + Precise Data Bus Error + [9:9] + + + NVIC_FAULT_STAT_IMPRE + Imprecise Data Bus Error + [10:10] + + + NVIC_FAULT_STAT_BUSTKE + Unstack Bus Fault + [11:11] + + + NVIC_FAULT_STAT_BSTKE + Stack Bus Fault + [12:12] + + + NVIC_FAULT_STAT_BFARV + Bus Fault Address Register Valid + [15:15] + + + NVIC_FAULT_STAT_UNDEF + Undefined Instruction Usage Fault + [16:16] + + + NVIC_FAULT_STAT_INVSTAT + Invalid State Usage Fault + [17:17] + + + NVIC_FAULT_STAT_INVPC + Invalid PC Load Usage Fault + [18:18] + + + NVIC_FAULT_STAT_NOCP + No Coprocessor Usage Fault + [19:19] + + + NVIC_FAULT_STAT_UNALIGN + Unaligned Access Usage Fault + [24:24] + + + NVIC_FAULT_STAT_DIV0 + Divide-by-Zero Usage Fault + [25:25] + + + + + HFAULT_STAT + Hard Fault Status + 0x00000D2C + + + NVIC_HFAULT_STAT_VECT + Vector Table Read Fault + [1:1] + + + NVIC_HFAULT_STAT_FORCED + Forced Hard Fault + [30:30] + + + NVIC_HFAULT_STAT_DBG + Debug Event + [31:31] + + + + + DEBUG_STAT + Debug Status Register + 0x00000D30 + + + NVIC_DEBUG_STAT_HALTED + Halt request + [0:0] + + + NVIC_DEBUG_STAT_BKPT + Breakpoint instruction + [1:1] + + + NVIC_DEBUG_STAT_DWTTRAP + DWT match + [2:2] + + + NVIC_DEBUG_STAT_VCATCH + Vector catch + [3:3] + + + NVIC_DEBUG_STAT_EXTRNL + EDBGRQ asserted + [4:4] + + + + + MM_ADDR + Memory Management Fault Address + 0x00000D34 + + + NVIC_MM_ADDR + Fault Address + [31:0] + + + + + FAULT_ADDR + Bus Fault Address + 0x00000D38 + + + NVIC_FAULT_ADDR + Fault Address + [31:0] + + + + + MPU_TYPE + MPU Type + 0x00000D90 + + + NVIC_MPU_TYPE_SEPARATE + Separate or Unified MPU + [0:0] + + + NVIC_MPU_TYPE_DREGION + Number of D Regions + [15:8] + + + NVIC_MPU_TYPE_IREGION + Number of I Regions + [23:16] + + + + + MPU_CTRL + MPU Control + 0x00000D94 + + + NVIC_MPU_CTRL_ENABLE + MPU Enable + [0:0] + + + NVIC_MPU_CTRL_HFNMIENA + MPU Enabled During Faults + [1:1] + + + NVIC_MPU_CTRL_PRIVDEFEN + MPU Default Region + [2:2] + + + + + MPU_NUMBER + MPU Region Number + 0x00000D98 + + + NVIC_MPU_NUMBER + MPU Region to Access + [2:0] + + + + + MPU_BASE + MPU Region Base Address + 0x00000D9C + + + NVIC_MPU_BASE_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR + MPU Region Attribute and Size + 0x00000DA0 + + + NVIC_MPU_ATTR_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR_SIZE_32B + Region size 32 bytes + 0x4 + + + NVIC_MPU_ATTR_SIZE_64B + Region size 64 bytes + 0x5 + + + NVIC_MPU_ATTR_SIZE_128B + Region size 128 bytes + 0x6 + + + NVIC_MPU_ATTR_SIZE_256B + Region size 256 bytes + 0x7 + + + NVIC_MPU_ATTR_SIZE_512B + Region size 512 bytes + 0x8 + + + NVIC_MPU_ATTR_SIZE_1K + Region size 1 Kbytes + 0x9 + + + NVIC_MPU_ATTR_SIZE_2K + Region size 2 Kbytes + 0xa + + + NVIC_MPU_ATTR_SIZE_4K + Region size 4 Kbytes + 0xb + + + NVIC_MPU_ATTR_SIZE_8K + Region size 8 Kbytes + 0xc + + + NVIC_MPU_ATTR_SIZE_16K + Region size 16 Kbytes + 0xd + + + NVIC_MPU_ATTR_SIZE_32K + Region size 32 Kbytes + 0xe + + + NVIC_MPU_ATTR_SIZE_64K + Region size 64 Kbytes + 0xf + + + NVIC_MPU_ATTR_SIZE_128K + Region size 128 Kbytes + 0x10 + + + NVIC_MPU_ATTR_SIZE_256K + Region size 256 Kbytes + 0x11 + + + NVIC_MPU_ATTR_SIZE_512K + Region size 512 Kbytes + 0x12 + + + NVIC_MPU_ATTR_SIZE_1M + Region size 1 Mbytes + 0x13 + + + NVIC_MPU_ATTR_SIZE_2M + Region size 2 Mbytes + 0x14 + + + NVIC_MPU_ATTR_SIZE_4M + Region size 4 Mbytes + 0x15 + + + NVIC_MPU_ATTR_SIZE_8M + Region size 8 Mbytes + 0x16 + + + NVIC_MPU_ATTR_SIZE_16M + Region size 16 Mbytes + 0x17 + + + NVIC_MPU_ATTR_SIZE_32M + Region size 32 Mbytes + 0x18 + + + NVIC_MPU_ATTR_SIZE_64M + Region size 64 Mbytes + 0x19 + + + NVIC_MPU_ATTR_SIZE_128M + Region size 128 Mbytes + 0x1a + + + NVIC_MPU_ATTR_SIZE_256M + Region size 256 Mbytes + 0x1b + + + NVIC_MPU_ATTR_SIZE_512M + Region size 512 Mbytes + 0x1c + + + NVIC_MPU_ATTR_SIZE_1G + Region size 1 Gbytes + 0x1d + + + NVIC_MPU_ATTR_SIZE_2G + Region size 2 Gbytes + 0x1e + + + NVIC_MPU_ATTR_SIZE_4G + Region size 4 Gbytes + 0x1f + + + + + NVIC_MPU_ATTR_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR_SRD_0 + Sub-region 0 disable + 0x1 + + + NVIC_MPU_ATTR_SRD_1 + Sub-region 1 disable + 0x2 + + + NVIC_MPU_ATTR_SRD_2 + Sub-region 2 disable + 0x4 + + + NVIC_MPU_ATTR_SRD_3 + Sub-region 3 disable + 0x8 + + + NVIC_MPU_ATTR_SRD_4 + Sub-region 4 disable + 0x10 + + + NVIC_MPU_ATTR_SRD_5 + Sub-region 5 disable + 0x20 + + + NVIC_MPU_ATTR_SRD_6 + Sub-region 6 disable + 0x40 + + + NVIC_MPU_ATTR_SRD_7 + Sub-region 7 disable + 0x80 + + + + + NVIC_MPU_ATTR_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR_AP_NO_NO + prv: no access, usr: no access + 0x0 + + + NVIC_MPU_ATTR_AP_RW_NO + prv: rw, usr: none + 0x1 + + + NVIC_MPU_ATTR_AP_RW_RO + prv: rw, usr: read-only + 0x2 + + + NVIC_MPU_ATTR_AP_RW_RW + prv: rw, usr: rw + 0x3 + + + NVIC_MPU_ATTR_AP_RO_NO + prv: ro, usr: none + 0x5 + + + NVIC_MPU_ATTR_AP_RO_RO + prv: ro, usr: ro + 0x6 + + + + + NVIC_MPU_ATTR_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE1 + MPU Region Base Address Alias 1 + 0x00000DA4 + + + NVIC_MPU_BASE1_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE1_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE1_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR1 + MPU Region Attribute and Size Alias 1 + 0x00000DA8 + + + NVIC_MPU_ATTR1_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR1_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR1_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR1_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR1_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR1_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR1_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR1_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR1_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE2 + MPU Region Base Address Alias 2 + 0x00000DAC + + + NVIC_MPU_BASE2_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE2_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE2_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR2 + MPU Region Attribute and Size Alias 2 + 0x00000DB0 + + + NVIC_MPU_ATTR2_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR2_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR2_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR2_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR2_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR2_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR2_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR2_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR2_XN + Instruction Access Disable + [28:28] + + + + + MPU_BASE3 + MPU Region Base Address Alias 3 + 0x00000DB4 + + + NVIC_MPU_BASE3_REGION + Region Number + [2:0] + + + NVIC_MPU_BASE3_VALID + Region Number Valid + [4:4] + + + NVIC_MPU_BASE3_ADDR + Base Address Mask + [31:5] + + + + + MPU_ATTR3 + MPU Region Attribute and Size Alias 3 + 0x00000DB8 + + + NVIC_MPU_ATTR3_ENABLE + Region Enable + [0:0] + + + NVIC_MPU_ATTR3_SIZE + Region Size Mask + [5:1] + + + NVIC_MPU_ATTR3_SRD + Subregion Disable Bits + [15:8] + + + NVIC_MPU_ATTR3_BUFFRABLE + Bufferable + [16:16] + + + NVIC_MPU_ATTR3_CACHEABLE + Cacheable + [17:17] + + + NVIC_MPU_ATTR3_SHAREABLE + Shareable + [18:18] + + + NVIC_MPU_ATTR3_TEX + Type Extension Mask + [21:19] + + + NVIC_MPU_ATTR3_AP + Access Privilege + [26:24] + + + NVIC_MPU_ATTR3_XN + Instruction Access Disable + [28:28] + + + + + DBG_CTRL + Debug Control and Status Reg + 0x00000DF0 + + + NVIC_DBG_CTRL_C_DEBUGEN + Enable debug + [0:0] + + + NVIC_DBG_CTRL_C_HALT + Halt the core + [1:1] + + + NVIC_DBG_CTRL_C_STEP + Step the core + [2:2] + + + NVIC_DBG_CTRL_C_MASKINT + Mask interrupts when stepping + [3:3] + + + NVIC_DBG_CTRL_C_SNAPSTALL + Breaks a stalled load/store + [5:5] + + + NVIC_DBG_CTRL_S_REGRDY + Register read/write available + [16:16] + + + NVIC_DBG_CTRL_S_HALT + Core status on halt + [17:17] + + + NVIC_DBG_CTRL_S_SLEEP + Core is sleeping + [18:18] + + + NVIC_DBG_CTRL_S_LOCKUP + Core is locked up + [19:19] + + + NVIC_DBG_CTRL_S_RETIRE_ST + Core has executed insruction since last read + [24:24] + + + NVIC_DBG_CTRL_S_RESET_ST + Core has reset since last read + [25:25] + + + + + DBG_XFER + Debug Core Reg. Transfer Select + 0x00000DF4 + + + NVIC_DBG_XFER_REG_SEL + Register + [4:0] + + + NVIC_DBG_XFER_REG_R0 + Register R0 + 0x0 + + + NVIC_DBG_XFER_REG_R1 + Register R1 + 0x1 + + + NVIC_DBG_XFER_REG_R2 + Register R2 + 0x2 + + + NVIC_DBG_XFER_REG_R3 + Register R3 + 0x3 + + + NVIC_DBG_XFER_REG_R4 + Register R4 + 0x4 + + + NVIC_DBG_XFER_REG_R5 + Register R5 + 0x5 + + + NVIC_DBG_XFER_REG_R6 + Register R6 + 0x6 + + + NVIC_DBG_XFER_REG_R7 + Register R7 + 0x7 + + + NVIC_DBG_XFER_REG_R8 + Register R8 + 0x8 + + + NVIC_DBG_XFER_REG_R9 + Register R9 + 0x9 + + + NVIC_DBG_XFER_REG_R10 + Register R10 + 0xa + + + NVIC_DBG_XFER_REG_R11 + Register R11 + 0xb + + + NVIC_DBG_XFER_REG_R12 + Register R12 + 0xc + + + NVIC_DBG_XFER_REG_R13 + Register R13 + 0xd + + + NVIC_DBG_XFER_REG_R14 + Register R14 + 0xe + + + NVIC_DBG_XFER_REG_R15 + Register R15 + 0xf + + + NVIC_DBG_XFER_REG_FLAGS + xPSR/Flags register + 0x10 + + + NVIC_DBG_XFER_REG_MSP + Main SP + 0x11 + + + NVIC_DBG_XFER_REG_PSP + Process SP + 0x12 + + + NVIC_DBG_XFER_REG_DSP + Deep SP + 0x13 + + + NVIC_DBG_XFER_REG_CFBP + Control/Fault/BasePri/PriMask + 0x14 + + + + + NVIC_DBG_XFER_REG_WNR + Write or not read + [16:16] + + + + + DBG_DATA + Debug Core Register Data + 0x00000DF8 + + + NVIC_DBG_DATA + Data temporary cache + [31:0] + + + + + DBG_INT + Debug Reset Interrupt Control + 0x00000DFC + + + NVIC_DBG_INT_RSTVCATCH + Reset vector catch + [0:0] + + + NVIC_DBG_INT_RSTPENDING + Core reset is pending + [1:1] + + + NVIC_DBG_INT_RSTPENDCLR + Clear pending core reset + [2:2] + + + NVIC_DBG_INT_RESET + Core reset status + [3:3] + + + NVIC_DBG_INT_MMERR + Debug trap on mem manage fault + [4:4] + + + NVIC_DBG_INT_NOCPERR + Debug trap on coprocessor error + [5:5] + + + NVIC_DBG_INT_CHKERR + Debug trap on usage fault check + [6:6] + + + NVIC_DBG_INT_STATERR + Debug trap on usage fault state + [7:7] + + + NVIC_DBG_INT_BUSERR + Debug trap on bus error + [8:8] + + + NVIC_DBG_INT_INTERR + Debug trap on interrupt errors + [9:9] + + + NVIC_DBG_INT_HARDERR + Debug trap on hard fault + [10:10] + + + + + SW_TRIG + Software Trigger Interrupt + 0x00000F00 + write-only + + + NVIC_SW_TRIG_INTID + Interrupt ID + [4:0] + write-only + + + + + + + + + FLASH + FLASH Memory Map for lm3s811 + 0x00000000 + + 0 + 0x00010000 + FLASH Memory + + + + SRAM + SRAM Memory Map for lm3s811 + 0x20000000 + + 0 + 0x00002000 + SRAM + + + +