8493 lines
320 KiB
XML
8493 lines
320 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
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<name>LM3S811</name>
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<version>7944</version>
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<description>ARM Cortex-M3 Stellaris Device</description>
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<addressUnitBits>8</addressUnitBits>
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<width>32</width>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0</resetValue>
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<resetMask>0</resetMask>
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<peripherals>
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<peripheral>
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<name>WATCHDOG0</name>
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<description>Register map for WATCHDOG0 peripheral</description>
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<groupName>WATCHDOG</groupName>
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<prependToName>WATCHDOG0</prependToName>
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<baseAddress>0x40000000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x00001000</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>LOAD</name>
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<description>Watchdog Load</description>
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<addressOffset>0x00000000</addressOffset>
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<fields>
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<field>
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<name>WDT_LOAD</name>
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<description>Watchdog Load Value</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>VALUE</name>
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<description>Watchdog Value</description>
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<addressOffset>0x00000004</addressOffset>
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<fields>
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<field>
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<name>WDT_VALUE</name>
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<description>Watchdog Value</description>
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<bitRange>[31:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>CTL</name>
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<description>Watchdog Control</description>
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<addressOffset>0x00000008</addressOffset>
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<fields>
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<field>
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<name>WDT_CTL_INTEN</name>
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<description>Watchdog Interrupt Enable</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>WDT_CTL_RESEN</name>
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<description>Watchdog Reset Enable</description>
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<bitRange>[1:1]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>ICR</name>
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<description>Watchdog Interrupt Clear</description>
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<addressOffset>0x0000000C</addressOffset>
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<access>write-only</access>
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<fields>
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<field>
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<name>WDT_ICR</name>
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<description>Watchdog Interrupt Clear</description>
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<bitRange>[31:0]</bitRange>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>RIS</name>
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<description>Watchdog Raw Interrupt Status</description>
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<addressOffset>0x00000010</addressOffset>
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<fields>
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<field>
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<name>WDT_RIS_WDTRIS</name>
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<description>Watchdog Raw Interrupt Status</description>
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<bitRange>[0:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>MIS</name>
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<description>Watchdog Masked Interrupt Status</description>
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<addressOffset>0x00000014</addressOffset>
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<fields>
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<field>
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<name>WDT_MIS_WDTMIS</name>
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<description>Watchdog Masked Interrupt Status</description>
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<bitRange>[0:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>TEST</name>
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<description>Watchdog Test</description>
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<addressOffset>0x00000418</addressOffset>
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<fields>
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<field>
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<name>WDT_TEST_STALL</name>
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<description>Watchdog Stall Enable</description>
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<bitRange>[8:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>LOCK</name>
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<description>Watchdog Lock</description>
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<addressOffset>0x00000C00</addressOffset>
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<fields>
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<field>
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<name>WDT_LOCK</name>
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<description>Watchdog Lock</description>
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<bitRange>[31:0]</bitRange>
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<enumeratedValues>
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<enumeratedValue>
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<name>WDT_LOCK_UNLOCKED</name>
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<description>Unlocked</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>WDT_LOCK_LOCKED</name>
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<description>Locked</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>WDT_LOCK_UNLOCK</name>
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<description>Unlocks the watchdog timer</description>
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<value>0x1acce551</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>GPIO_PORTA</name>
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<description>Register map for GPIO_PORTA peripheral</description>
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<groupName>GPIO_PORT</groupName>
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<prependToName>GPIO_PORTA</prependToName>
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<baseAddress>0x40004000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x00001000</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>DATA</name>
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<description>GPIO Data</description>
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<addressOffset>0x000003FC</addressOffset>
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</register>
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<register>
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<name>DIR</name>
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<description>GPIO Direction</description>
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<addressOffset>0x00000400</addressOffset>
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</register>
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<register>
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<name>IS</name>
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<description>GPIO Interrupt Sense</description>
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<addressOffset>0x00000404</addressOffset>
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</register>
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<register>
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<name>IBE</name>
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<description>GPIO Interrupt Both Edges</description>
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<addressOffset>0x00000408</addressOffset>
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</register>
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<register>
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<name>IEV</name>
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<description>GPIO Interrupt Event</description>
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<addressOffset>0x0000040C</addressOffset>
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</register>
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<register>
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<name>IM</name>
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<description>GPIO Interrupt Mask</description>
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<addressOffset>0x00000410</addressOffset>
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</register>
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<register>
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<name>RIS</name>
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<description>GPIO Raw Interrupt Status</description>
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<addressOffset>0x00000414</addressOffset>
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</register>
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<register>
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<name>MIS</name>
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<description>GPIO Masked Interrupt Status</description>
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<addressOffset>0x00000418</addressOffset>
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</register>
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<register>
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<name>ICR</name>
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<description>GPIO Interrupt Clear</description>
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<addressOffset>0x0000041C</addressOffset>
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<access>write-only</access>
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</register>
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<register>
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<name>AFSEL</name>
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<description>GPIO Alternate Function Select</description>
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<addressOffset>0x00000420</addressOffset>
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</register>
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<register>
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<name>DR2R</name>
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<description>GPIO 2-mA Drive Select</description>
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<addressOffset>0x00000500</addressOffset>
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</register>
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<register>
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<name>DR4R</name>
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<description>GPIO 4-mA Drive Select</description>
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<addressOffset>0x00000504</addressOffset>
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</register>
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<register>
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<name>DR8R</name>
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<description>GPIO 8-mA Drive Select</description>
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<addressOffset>0x00000508</addressOffset>
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</register>
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<register>
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<name>ODR</name>
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<description>GPIO Open Drain Select</description>
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<addressOffset>0x0000050C</addressOffset>
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</register>
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<register>
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<name>PUR</name>
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<description>GPIO Pull-Up Select</description>
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<addressOffset>0x00000510</addressOffset>
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</register>
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<register>
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<name>PDR</name>
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<description>GPIO Pull-Down Select</description>
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<addressOffset>0x00000514</addressOffset>
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</register>
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<register>
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<name>SLR</name>
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<description>GPIO Slew Rate Control Select</description>
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<addressOffset>0x00000518</addressOffset>
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</register>
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<register>
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<name>DEN</name>
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<description>GPIO Digital Enable</description>
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<addressOffset>0x0000051C</addressOffset>
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</register>
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</registers>
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</peripheral>
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<peripheral derivedFrom="GPIO_PORTA">
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<name>GPIO_PORTB</name>
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<prependToName>GPIO_PORTB</prependToName>
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<baseAddress>0x40005000</baseAddress>
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</peripheral>
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<peripheral derivedFrom="GPIO_PORTA">
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<name>GPIO_PORTC</name>
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<prependToName>GPIO_PORTC</prependToName>
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<baseAddress>0x40006000</baseAddress>
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</peripheral>
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<peripheral derivedFrom="GPIO_PORTA">
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<name>GPIO_PORTD</name>
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<prependToName>GPIO_PORTD</prependToName>
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<baseAddress>0x40007000</baseAddress>
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</peripheral>
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<peripheral>
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<name>SSI0</name>
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<description>Register map for SSI0 peripheral</description>
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<groupName>SSI</groupName>
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<prependToName>SSI0</prependToName>
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<baseAddress>0x40008000</baseAddress>
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<addressBlock>
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<offset>0</offset>
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<size>0x00001000</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CR0</name>
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<description>SSI Control 0</description>
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<addressOffset>0x00000000</addressOffset>
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<fields>
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<field>
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<name>SSI_CR0_DSS</name>
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<description>SSI Data Size Select</description>
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<bitRange>[3:0]</bitRange>
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<enumeratedValues>
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<enumeratedValue>
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<name>SSI_CR0_DSS_4</name>
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<description>4-bit data</description>
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<value>0x3</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_5</name>
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<description>5-bit data</description>
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<value>0x4</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_6</name>
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<description>6-bit data</description>
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<value>0x5</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_7</name>
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<description>7-bit data</description>
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<value>0x6</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_8</name>
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<description>8-bit data</description>
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<value>0x7</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_9</name>
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<description>9-bit data</description>
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<value>0x8</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_10</name>
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<description>10-bit data</description>
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<value>0x9</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_11</name>
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<description>11-bit data</description>
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<value>0xa</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_12</name>
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<description>12-bit data</description>
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<value>0xb</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_13</name>
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<description>13-bit data</description>
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<value>0xc</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_14</name>
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<description>14-bit data</description>
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<value>0xd</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_15</name>
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<description>15-bit data</description>
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<value>0xe</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_DSS_16</name>
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<description>16-bit data</description>
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<value>0xf</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SSI_CR0_FRF</name>
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<description>SSI Frame Format Select</description>
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<bitRange>[5:4]</bitRange>
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<enumeratedValues>
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<enumeratedValue>
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<name>SSI_CR0_FRF_MOTO</name>
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<description>Freescale SPI Frame Format</description>
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<value>0x0</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_FRF_TI</name>
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<description>Texas Instruments Synchronous Serial Frame Format</description>
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<value>0x1</value>
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</enumeratedValue>
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<enumeratedValue>
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<name>SSI_CR0_FRF_NMW</name>
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<description>MICROWIRE Frame Format</description>
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<value>0x2</value>
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</enumeratedValue>
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</enumeratedValues>
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</field>
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<field>
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<name>SSI_CR0_SPO</name>
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<description>SSI Serial Clock Polarity</description>
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<bitRange>[6:6]</bitRange>
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</field>
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<field>
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<name>SSI_CR0_SPH</name>
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<description>SSI Serial Clock Phase</description>
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<bitRange>[7:7]</bitRange>
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</field>
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<field>
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<name>SSI_CR0_SCR</name>
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<description>SSI Serial Clock Rate</description>
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<bitRange>[15:8]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>CR1</name>
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<description>SSI Control 1</description>
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<addressOffset>0x00000004</addressOffset>
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<fields>
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<field>
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<name>SSI_CR1_LBM</name>
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<description>SSI Loopback Mode</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>SSI_CR1_SSE</name>
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<description>SSI Synchronous Serial Port Enable</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>SSI_CR1_MS</name>
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<description>SSI Master/Slave Select</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>SSI_CR1_SOD</name>
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<description>SSI Slave Mode Output Disable</description>
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<bitRange>[3:3]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>DR</name>
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<description>SSI Data</description>
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<addressOffset>0x00000008</addressOffset>
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<fields>
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<field>
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<name>SSI_DR_DATA</name>
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<description>SSI Receive/Transmit Data</description>
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<bitRange>[15:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>SR</name>
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<description>SSI Status</description>
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<addressOffset>0x0000000C</addressOffset>
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<fields>
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<field>
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<name>SSI_SR_TFE</name>
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<description>SSI Transmit FIFO Empty</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>SSI_SR_TNF</name>
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<description>SSI Transmit FIFO Not Full</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>SSI_SR_RNE</name>
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<description>SSI Receive FIFO Not Empty</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>SSI_SR_RFF</name>
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<description>SSI Receive FIFO Full</description>
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<bitRange>[3:3]</bitRange>
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</field>
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<field>
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<name>SSI_SR_BSY</name>
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<description>SSI Busy Bit</description>
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<bitRange>[4:4]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>CPSR</name>
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<description>SSI Clock Prescale</description>
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<addressOffset>0x00000010</addressOffset>
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<fields>
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<field>
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<name>SSI_CPSR_CPSDVSR</name>
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<description>SSI Clock Prescale Divisor</description>
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<bitRange>[7:0]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>IM</name>
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<description>SSI Interrupt Mask</description>
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<addressOffset>0x00000014</addressOffset>
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<fields>
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<field>
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<name>SSI_IM_RORIM</name>
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<description>SSI Receive Overrun Interrupt Mask</description>
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<bitRange>[0:0]</bitRange>
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</field>
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<field>
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<name>SSI_IM_RTIM</name>
|
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<description>SSI Receive Time-Out Interrupt Mask</description>
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<bitRange>[1:1]</bitRange>
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</field>
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<field>
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<name>SSI_IM_RXIM</name>
|
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<description>SSI Receive FIFO Interrupt Mask</description>
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<bitRange>[2:2]</bitRange>
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</field>
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<field>
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<name>SSI_IM_TXIM</name>
|
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<description>SSI Transmit FIFO Interrupt Mask</description>
|
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<bitRange>[3:3]</bitRange>
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</field>
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</fields>
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</register>
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<register>
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<name>RIS</name>
|
|
<description>SSI Raw Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_RIS_RORRIS</name>
|
|
<description>SSI Receive Overrun Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_RTRIS</name>
|
|
<description>SSI Receive Time-Out Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_RXRIS</name>
|
|
<description>SSI Receive FIFO Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_RIS_TXRIS</name>
|
|
<description>SSI Transmit FIFO Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>SSI Masked Interrupt Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_MIS_RORMIS</name>
|
|
<description>SSI Receive Overrun Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_RTMIS</name>
|
|
<description>SSI Receive Time-Out Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_RXMIS</name>
|
|
<description>SSI Receive FIFO Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SSI_MIS_TXMIS</name>
|
|
<description>SSI Transmit FIFO Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>SSI Interrupt Clear</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>SSI_ICR_RORIC</name>
|
|
<description>SSI Receive Overrun Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI_ICR_RTIC</name>
|
|
<description>SSI Receive Time-Out Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART0</name>
|
|
<description>Register map for UART0 peripheral</description>
|
|
<groupName>UART</groupName>
|
|
<prependToName>UART0</prependToName>
|
|
<baseAddress>0x4000C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>UART Data</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_DR_DATA</name>
|
|
<description>Data Transmitted or Received</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_FE</name>
|
|
<description>UART Framing Error</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_PE</name>
|
|
<description>UART Parity Error</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_BE</name>
|
|
<description>UART Break Error</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_DR_OE</name>
|
|
<description>UART Overrun Error</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSR</name>
|
|
<description>UART Receive Status/Error Clear</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_RSR_FE</name>
|
|
<description>UART Framing Error</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_PE</name>
|
|
<description>UART Parity Error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_BE</name>
|
|
<description>UART Break Error</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RSR_OE</name>
|
|
<description>UART Overrun Error</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<description>UART Receive Status/Error Clear</description>
|
|
<alternateGroup>UART_ALT</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_ECR_DATA</name>
|
|
<description>Error Clear</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<description>UART Flag</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_FR_BUSY</name>
|
|
<description>UART Busy</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_RXFE</name>
|
|
<description>UART Receive FIFO Empty</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_TXFF</name>
|
|
<description>UART Transmit FIFO Full</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_RXFF</name>
|
|
<description>UART Receive FIFO Full</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_FR_TXFE</name>
|
|
<description>UART Transmit FIFO Empty</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IBRD</name>
|
|
<description>UART Integer Baud-Rate Divisor</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IBRD_DIVINT</name>
|
|
<description>Integer Baud-Rate Divisor</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FBRD</name>
|
|
<description>UART Fractional Baud-Rate Divisor</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_FBRD_DIVFRAC</name>
|
|
<description>Fractional Baud-Rate Divisor</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCRH</name>
|
|
<description>UART Line Control</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_LCRH_BRK</name>
|
|
<description>UART Send Break</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_PEN</name>
|
|
<description>UART Parity Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_EPS</name>
|
|
<description>UART Even Parity Select</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_STP2</name>
|
|
<description>UART Two Stop Bits Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_FEN</name>
|
|
<description>UART Enable FIFOs</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_WLEN</name>
|
|
<description>UART Word Length</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_5</name>
|
|
<description>5 bits (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_6</name>
|
|
<description>6 bits</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_7</name>
|
|
<description>7 bits</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_LCRH_WLEN_8</name>
|
|
<description>8 bits</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART_LCRH_SPS</name>
|
|
<description>UART Stick Parity Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>UART Control</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_CTL_UARTEN</name>
|
|
<description>UART Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_LBE</name>
|
|
<description>UART Loop Back Enable</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_TXE</name>
|
|
<description>UART Transmit Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_CTL_RXE</name>
|
|
<description>UART Receive Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFLS</name>
|
|
<description>UART Interrupt FIFO Level Select</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IFLS_TX</name>
|
|
<description>UART Transmit Interrupt FIFO Level Select</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX1_8</name>
|
|
<description>TX FIFO &lt;= 1/8 full</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX2_8</name>
|
|
<description>TX FIFO &lt;= 1/4 full</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX4_8</name>
|
|
<description>TX FIFO &lt;= 1/2 full (default)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX6_8</name>
|
|
<description>TX FIFO &lt;= 3/4 full</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_TX7_8</name>
|
|
<description>TX FIFO &lt;= 7/8 full</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>UART_IFLS_RX</name>
|
|
<description>UART Receive Interrupt FIFO Level Select</description>
|
|
<bitRange>[5:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX1_8</name>
|
|
<description>RX FIFO >= 1/8 full</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX2_8</name>
|
|
<description>RX FIFO >= 1/4 full</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX4_8</name>
|
|
<description>RX FIFO >= 1/2 full (default)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX6_8</name>
|
|
<description>RX FIFO >= 3/4 full</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>UART_IFLS_RX7_8</name>
|
|
<description>RX FIFO >= 7/8 full</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>UART Interrupt Mask</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_IM_RXIM</name>
|
|
<description>UART Receive Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_TXIM</name>
|
|
<description>UART Transmit Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_RTIM</name>
|
|
<description>UART Receive Time-Out Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_FEIM</name>
|
|
<description>UART Framing Error Interrupt Mask</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_PEIM</name>
|
|
<description>UART Parity Error Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_BEIM</name>
|
|
<description>UART Break Error Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_IM_OEIM</name>
|
|
<description>UART Overrun Error Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>UART Raw Interrupt Status</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_RIS_RXRIS</name>
|
|
<description>UART Receive Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_TXRIS</name>
|
|
<description>UART Transmit Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_RTRIS</name>
|
|
<description>UART Receive Time-Out Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_FERIS</name>
|
|
<description>UART Framing Error Raw Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_PERIS</name>
|
|
<description>UART Parity Error Raw Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_BERIS</name>
|
|
<description>UART Break Error Raw Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_RIS_OERIS</name>
|
|
<description>UART Overrun Error Raw Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>UART Masked Interrupt Status</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>UART_MIS_RXMIS</name>
|
|
<description>UART Receive Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_TXMIS</name>
|
|
<description>UART Transmit Masked Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_RTMIS</name>
|
|
<description>UART Receive Time-Out Masked Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_FEMIS</name>
|
|
<description>UART Framing Error Masked Interrupt Status</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_PEMIS</name>
|
|
<description>UART Parity Error Masked Interrupt Status</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_BEMIS</name>
|
|
<description>UART Break Error Masked Interrupt Status</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>UART_MIS_OEMIS</name>
|
|
<description>UART Overrun Error Masked Interrupt Status</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>UART Interrupt Clear</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>UART_ICR_RXIC</name>
|
|
<description>Receive Interrupt Clear</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_TXIC</name>
|
|
<description>Transmit Interrupt Clear</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_RTIC</name>
|
|
<description>Receive Time-Out Interrupt Clear</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_FEIC</name>
|
|
<description>Framing Error Interrupt Clear</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_PEIC</name>
|
|
<description>Parity Error Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_BEIC</name>
|
|
<description>Break Error Interrupt Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UART_ICR_OEIC</name>
|
|
<description>Overrun Error Interrupt Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART0">
|
|
<name>UART1</name>
|
|
<prependToName>UART1</prependToName>
|
|
<baseAddress>0x4000D000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C0</name>
|
|
<description>Register map for I2C0 peripheral</description>
|
|
<groupName>I2C</groupName>
|
|
<prependToName>I2C0</prependToName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MSA</name>
|
|
<description>I2C Master Slave Address</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MSA_RS</name>
|
|
<description>Receive not send</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MSA_SA</name>
|
|
<description>I2C Slave Address</description>
|
|
<bitRange>[7:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOAR</name>
|
|
<description>I2C Slave Own Address</description>
|
|
<addressOffset>0x00000800</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SOAR_OAR</name>
|
|
<description>I2C Slave Own Address</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCSR</name>
|
|
<description>I2C Slave Control/Status</description>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SCSR_RREQ</name>
|
|
<description>Receive Request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_TREQ</name>
|
|
<description>Transmit Request</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_SCSR_FBR</name>
|
|
<description>First Byte Received</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCSR</name>
|
|
<description>I2C Slave Control/Status</description>
|
|
<alternateGroup>I2C0_ALT</alternateGroup>
|
|
<addressOffset>0x00000804</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SCSR_DA</name>
|
|
<description>Device Active</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCS</name>
|
|
<description>I2C Master Control/Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCS_RUN</name>
|
|
<description>I2C Master Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_START</name>
|
|
<description>Generate START</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ADRACK</name>
|
|
<description>Acknowledge Address</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ACK</name>
|
|
<description>Data Acknowledge Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ARBLST</name>
|
|
<description>Arbitration Lost</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_IDLE</name>
|
|
<description>I2C Idle</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_BUSBSY</name>
|
|
<description>Bus Busy</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCS</name>
|
|
<description>I2C Master Control/Status</description>
|
|
<alternateGroup>I2C0_ALT</alternateGroup>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCS_BUSY</name>
|
|
<description>I2C Busy</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_ERROR</name>
|
|
<description>Error</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_STOP</name>
|
|
<description>Generate STOP</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCS_DATACK</name>
|
|
<description>Acknowledge Data</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDR</name>
|
|
<description>I2C Slave Data</description>
|
|
<addressOffset>0x00000808</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SDR_DATA</name>
|
|
<description>Data for Transfer</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDR</name>
|
|
<description>I2C Master Data</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MDR_DATA</name>
|
|
<description>Data Transferred</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MTPR</name>
|
|
<description>I2C Master Timer Period</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MTPR_TPR</name>
|
|
<description>SCL Clock Period</description>
|
|
<bitRange>[6:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIMR</name>
|
|
<description>I2C Slave Interrupt Mask</description>
|
|
<addressOffset>0x0000080C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SIMR_DATAIM</name>
|
|
<description>Data Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRIS</name>
|
|
<description>I2C Slave Raw Interrupt Status</description>
|
|
<addressOffset>0x00000810</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SRIS_DATARIS</name>
|
|
<description>Data Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIMR</name>
|
|
<description>I2C Master Interrupt Mask</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MIMR_IM</name>
|
|
<description>Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MRIS</name>
|
|
<description>I2C Master Raw Interrupt Status</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MRIS_RIS</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMIS</name>
|
|
<description>I2C Slave Masked Interrupt Status</description>
|
|
<addressOffset>0x00000814</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SMIS_DATAMIS</name>
|
|
<description>Data Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SICR</name>
|
|
<description>I2C Slave Interrupt Clear</description>
|
|
<addressOffset>0x00000818</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_SICR_DATAIC</name>
|
|
<description>Data Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMIS</name>
|
|
<description>I2C Master Masked Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MMIS_MIS</name>
|
|
<description>Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MICR</name>
|
|
<description>I2C Master Interrupt Clear</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MICR_IC</name>
|
|
<description>Interrupt Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>I2C Master Configuration</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_MCR_LPBK</name>
|
|
<description>I2C Loopback</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCR_MFE</name>
|
|
<description>I2C Master Function Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>I2C_MCR_SFE</name>
|
|
<description>I2C Slave Function Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIO_PORTA">
|
|
<name>GPIO_PORTE</name>
|
|
<prependToName>GPIO_PORTE</prependToName>
|
|
<baseAddress>0x40024000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWM0</name>
|
|
<description>Register map for PWM0 peripheral</description>
|
|
<groupName>PWM</groupName>
|
|
<prependToName>PWM0</prependToName>
|
|
<baseAddress>0x40028000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>PWM Master Control</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC0</name>
|
|
<description>Update PWM Generator 0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC1</name>
|
|
<description>Update PWM Generator 1</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_CTL_GLOBALSYNC2</name>
|
|
<description>Update PWM Generator 2</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYNC</name>
|
|
<description>PWM Time Base Sync</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC0</name>
|
|
<description>Reset Generator 0 Counter</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC1</name>
|
|
<description>Reset Generator 1 Counter</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_SYNC_SYNC2</name>
|
|
<description>Reset Generator 2 Counter</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENABLE</name>
|
|
<description>PWM Output Enable</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM0EN</name>
|
|
<description>PWM0 Output Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM1EN</name>
|
|
<description>PWM1 Output Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM2EN</name>
|
|
<description>PWM2 Output Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM3EN</name>
|
|
<description>PWM3 Output Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM4EN</name>
|
|
<description>PWM4 Output Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ENABLE_PWM5EN</name>
|
|
<description>PWM5 Output Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INVERT</name>
|
|
<description>PWM Output Inversion</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_INVERT_PWM0INV</name>
|
|
<description>Invert PWM0 Signal</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM1INV</name>
|
|
<description>Invert PWM1 Signal</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM2INV</name>
|
|
<description>Invert PWM2 Signal</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM3INV</name>
|
|
<description>Invert PWM3 Signal</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM4INV</name>
|
|
<description>Invert PWM4 Signal</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INVERT_PWM5INV</name>
|
|
<description>Invert PWM5 Signal</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULT</name>
|
|
<description>PWM Output Fault</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT0</name>
|
|
<description>PWM0 Fault</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT1</name>
|
|
<description>PWM1 Fault</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT2</name>
|
|
<description>PWM2 Fault</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT3</name>
|
|
<description>PWM3 Fault</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT4</name>
|
|
<description>PWM4 Fault</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_FAULT_FAULT5</name>
|
|
<description>PWM5 Fault</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTEN</name>
|
|
<description>PWM Interrupt Enable</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM0</name>
|
|
<description>PWM0 Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM1</name>
|
|
<description>PWM1 Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTPWM2</name>
|
|
<description>PWM2 Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_INTEN_INTFAULT</name>
|
|
<description>Fault Interrupt Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>PWM Raw Interrupt Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM0</name>
|
|
<description>PWM0 Interrupt Asserted</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM1</name>
|
|
<description>PWM1 Interrupt Asserted</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTPWM2</name>
|
|
<description>PWM2 Interrupt Asserted</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_RIS_INTFAULT</name>
|
|
<description>Fault Interrupt Asserted</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISC</name>
|
|
<description>PWM Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM0</name>
|
|
<description>PWM0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM1</name>
|
|
<description>PWM1 Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTPWM2</name>
|
|
<description>PWM2 Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_ISC_INTFAULT</name>
|
|
<description>Fault Interrupt Asserted</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STATUS</name>
|
|
<description>PWM Status</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_0_CTL</name>
|
|
<description>PWM0 Control</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_CTL_ENABLE</name>
|
|
<description>PWM Block Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_CTL_MODE</name>
|
|
<description>Counter Mode</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_CTL_DEBUG</name>
|
|
<description>Debug Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_CTL_LOADUPD</name>
|
|
<description>Load Register Update Mode</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_CTL_CMPAUPD</name>
|
|
<description>Comparator A Update Mode</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_CTL_CMPBUPD</name>
|
|
<description>Comparator B Update Mode</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_INTEN</name>
|
|
<description>PWM0 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCNTZERO</name>
|
|
<description>Interrupt for Counter=0</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCNTLOAD</name>
|
|
<description>Interrupt for Counter=PWMnLOAD</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCMPAU</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCMPAD</name>
|
|
<description>Interrupt for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCMPBU</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_INTCMPBD</name>
|
|
<description>Interrupt for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCNTZERO</name>
|
|
<description>Trigger for Counter=0</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCNTLOAD</name>
|
|
<description>Trigger for Counter=PWMnLOAD</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCMPAU</name>
|
|
<description>Trigger for Counter=PWMnCMPA Up</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCMPAD</name>
|
|
<description>Trigger for Counter=PWMnCMPA Down</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCMPBU</name>
|
|
<description>Trigger for Counter=PWMnCMPB Up</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_INTEN_TRCMPBD</name>
|
|
<description>Trigger for Counter=PWMnCMPB Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_RIS</name>
|
|
<description>PWM0 Raw Interrupt Status</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_RIS_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_ISC</name>
|
|
<description>PWM0 Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCNTZERO</name>
|
|
<description>Counter=0 Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCNTLOAD</name>
|
|
<description>Counter=Load Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCMPAU</name>
|
|
<description>Comparator A Up Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCMPAD</name>
|
|
<description>Comparator A Down Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCMPBU</name>
|
|
<description>Comparator B Up Interrupt</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_ISC_INTCMPBD</name>
|
|
<description>Comparator B Down Interrupt</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_LOAD</name>
|
|
<description>PWM0 Load</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_LOAD</name>
|
|
<description>Counter Load Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_COUNT</name>
|
|
<description>PWM0 Counter</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_COUNT</name>
|
|
<description>Counter Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_CMPA</name>
|
|
<description>PWM0 Compare A</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_CMPA</name>
|
|
<description>Comparator A Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_CMPB</name>
|
|
<description>PWM0 Compare B</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_CMPB</name>
|
|
<description>Comparator B Value</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_GENA</name>
|
|
<description>PWM0 Generator A Control</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTZERO_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTZERO_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTZERO_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTLOAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTLOAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBU_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENA_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBD_INV</name>
|
|
<description>Invert pwmA</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmA Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENA_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmA High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_GENB</name>
|
|
<description>PWM0 Generator B Control</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTZERO</name>
|
|
<description>Action for Counter=0</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTZERO_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTZERO_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTZERO_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTZERO_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTLOAD</name>
|
|
<description>Action for Counter=LOAD</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTLOAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTLOAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTLOAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTLOAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTCMPAU</name>
|
|
<description>Action for Comparator A Up</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTCMPAD</name>
|
|
<description>Action for Comparator A Down</description>
|
|
<bitRange>[7:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPAD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTCMPBU</name>
|
|
<description>Action for Comparator B Up</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBU_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBU_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBU_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBU_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>PWM_X_GENB_ACTCMPBD</name>
|
|
<description>Action for Comparator B Down</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBD_NONE</name>
|
|
<description>Do nothing</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBD_INV</name>
|
|
<description>Invert pwmB</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBD_ZERO</name>
|
|
<description>Drive pwmB Low</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>PWM_X_GENB_ACTCMPBD_ONE</name>
|
|
<description>Drive pwmB High</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBCTL</name>
|
|
<description>PWM0 Dead-Band Control</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_DBCTL_ENABLE</name>
|
|
<description>Dead-Band Generator Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBRISE</name>
|
|
<description>PWM0 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_DBRISE_DELAY</name>
|
|
<description>Dead-Band Rise Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_0_DBFALL</name>
|
|
<description>PWM0 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x00000070</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>PWM_X_DBFALL_DELAY</name>
|
|
<description>Dead-Band Fall Delay</description>
|
|
<bitRange>[11:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>_1_CTL</name>
|
|
<description>PWM1 Control</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_INTEN</name>
|
|
<description>PWM1 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_RIS</name>
|
|
<description>PWM1 Raw Interrupt Status</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_ISC</name>
|
|
<description>PWM1 Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_LOAD</name>
|
|
<description>PWM1 Load</description>
|
|
<addressOffset>0x00000090</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_COUNT</name>
|
|
<description>PWM1 Counter</description>
|
|
<addressOffset>0x00000094</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_CMPA</name>
|
|
<description>PWM1 Compare A</description>
|
|
<addressOffset>0x00000098</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_CMPB</name>
|
|
<description>PWM1 Compare B</description>
|
|
<addressOffset>0x0000009C</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_GENA</name>
|
|
<description>PWM1 Generator A Control</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_GENB</name>
|
|
<description>PWM1 Generator B Control</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBCTL</name>
|
|
<description>PWM1 Dead-Band Control</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBRISE</name>
|
|
<description>PWM1 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_1_DBFALL</name>
|
|
<description>PWM1 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x000000B0</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_CTL</name>
|
|
<description>PWM2 Control</description>
|
|
<addressOffset>0x000000C0</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_INTEN</name>
|
|
<description>PWM2 Interrupt and Trigger Enable</description>
|
|
<addressOffset>0x000000C4</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_RIS</name>
|
|
<description>PWM2 Raw Interrupt Status</description>
|
|
<addressOffset>0x000000C8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_ISC</name>
|
|
<description>PWM2 Interrupt Status and Clear</description>
|
|
<addressOffset>0x000000CC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_LOAD</name>
|
|
<description>PWM2 Load</description>
|
|
<addressOffset>0x000000D0</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_COUNT</name>
|
|
<description>PWM2 Counter</description>
|
|
<addressOffset>0x000000D4</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_CMPA</name>
|
|
<description>PWM2 Compare A</description>
|
|
<addressOffset>0x000000D8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_CMPB</name>
|
|
<description>PWM2 Compare B</description>
|
|
<addressOffset>0x000000DC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_GENA</name>
|
|
<description>PWM2 Generator A Control</description>
|
|
<addressOffset>0x000000E0</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_GENB</name>
|
|
<description>PWM2 Generator B Control</description>
|
|
<addressOffset>0x000000E4</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBCTL</name>
|
|
<description>PWM2 Dead-Band Control</description>
|
|
<addressOffset>0x000000E8</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBRISE</name>
|
|
<description>PWM2 Dead-Band Rising-Edge Delay</description>
|
|
<addressOffset>0x000000EC</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>_2_DBFALL</name>
|
|
<description>PWM2 Dead-Band Falling-Edge-Delay</description>
|
|
<addressOffset>0x000000F0</addressOffset>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIMER0</name>
|
|
<description>Register map for TIMER0 peripheral</description>
|
|
<groupName>TIMER</groupName>
|
|
<prependToName>TIMER0</prependToName>
|
|
<baseAddress>0x40030000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CFG</name>
|
|
<description>GPTM Configuration</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_CFG</name>
|
|
<description>GPTM Configuration</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_32_BIT_TIMER</name>
|
|
<description>32-bit timer configuration</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_32_BIT_RTC</name>
|
|
<description>32-bit real-time clock (RTC) counter configuration</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CFG_16_BIT</name>
|
|
<description>16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMR</name>
|
|
<description>GPTM Timer A Mode</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAMR_TAMR</name>
|
|
<description>GPTM Timer A Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_1_SHOT</name>
|
|
<description>One-Shot Timer mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_PERIOD</name>
|
|
<description>Periodic Timer mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TAMR_TAMR_CAP</name>
|
|
<description>Capture mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TACMR</name>
|
|
<description>GPTM Timer A Capture Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMR_TAAMS</name>
|
|
<description>GPTM Timer A Alternate Mode Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBMR</name>
|
|
<description>GPTM Timer B Mode</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBMR_TBMR</name>
|
|
<description>GPTM Timer B Mode</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_1_SHOT</name>
|
|
<description>One-Shot Timer mode</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_PERIOD</name>
|
|
<description>Periodic Timer mode</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_TBMR_TBMR_CAP</name>
|
|
<description>Capture mode</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBCMR</name>
|
|
<description>GPTM Timer B Capture Mode</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TBMR_TBAMS</name>
|
|
<description>GPTM Timer B Alternate Mode Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL</name>
|
|
<description>GPTM Control</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_CTL_TAEN</name>
|
|
<description>GPTM Timer A Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TASTALL</name>
|
|
<description>GPTM Timer A Stall Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAEVENT</name>
|
|
<description>GPTM Timer A Event Mode</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_POS</name>
|
|
<description>Positive edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_NEG</name>
|
|
<description>Negative edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TAEVENT_BOTH</name>
|
|
<description>Both edges</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_RTCEN</name>
|
|
<description>GPTM RTC Enable</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAOTE</name>
|
|
<description>GPTM Timer A Output Trigger Enable</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TAPWML</name>
|
|
<description>GPTM Timer A PWM Output Level</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBEN</name>
|
|
<description>GPTM Timer B Enable</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBSTALL</name>
|
|
<description>GPTM Timer B Stall Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBEVENT</name>
|
|
<description>GPTM Timer B Event Mode</description>
|
|
<bitRange>[11:10]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_POS</name>
|
|
<description>Positive edge</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_NEG</name>
|
|
<description>Negative edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>TIMER_CTL_TBEVENT_BOTH</name>
|
|
<description>Both edges</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBOTE</name>
|
|
<description>GPTM Timer B Output Trigger Enable</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_CTL_TBPWML</name>
|
|
<description>GPTM Timer B PWM Output Level</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<description>GPTM Interrupt Mask</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_IMR_TATOIM</name>
|
|
<description>GPTM Timer A Time-Out Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CAMIM</name>
|
|
<description>GPTM Capture A Match Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CAEIM</name>
|
|
<description>GPTM Capture A Event Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_RTCIM</name>
|
|
<description>GPTM RTC Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_TBTOIM</name>
|
|
<description>GPTM Timer B Time-Out Interrupt Mask</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CBMIM</name>
|
|
<description>GPTM Capture B Match Interrupt Mask</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_IMR_CBEIM</name>
|
|
<description>GPTM Capture B Event Interrupt Mask</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>GPTM Raw Interrupt Status</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_RIS_TATORIS</name>
|
|
<description>GPTM Timer A Time-Out Raw Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CAMRIS</name>
|
|
<description>GPTM Capture A Match Raw Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CAERIS</name>
|
|
<description>GPTM Capture A Event Raw Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_RTCRIS</name>
|
|
<description>GPTM RTC Raw Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_TBTORIS</name>
|
|
<description>GPTM Timer B Time-Out Raw Interrupt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CBMRIS</name>
|
|
<description>GPTM Capture B Match Raw Interrupt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_RIS_CBERIS</name>
|
|
<description>GPTM Capture B Event Raw Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MIS</name>
|
|
<description>GPTM Masked Interrupt Status</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_MIS_TATOMIS</name>
|
|
<description>GPTM Timer A Time-Out Masked Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CAMMIS</name>
|
|
<description>GPTM Capture A Match Masked Interrupt</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CAEMIS</name>
|
|
<description>GPTM Capture A Event Masked Interrupt</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_RTCMIS</name>
|
|
<description>GPTM RTC Masked Interrupt</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_TBTOMIS</name>
|
|
<description>GPTM Timer B Time-Out Masked Interrupt</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CBMMIS</name>
|
|
<description>GPTM Capture B Match Masked Interrupt</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_MIS_CBEMIS</name>
|
|
<description>GPTM Capture B Event Masked Interrupt</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<description>GPTM Interrupt Clear</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_ICR_TATOCINT</name>
|
|
<description>GPTM Timer A Time-Out Raw Interrupt</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CAMCINT</name>
|
|
<description>GPTM Capture A Match Interrupt Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CAECINT</name>
|
|
<description>GPTM Capture A Event Interrupt Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_RTCCINT</name>
|
|
<description>GPTM RTC Interrupt Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_TBTOCINT</name>
|
|
<description>GPTM Timer B Time-Out Interrupt Clear</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CBMCINT</name>
|
|
<description>GPTM Capture B Match Interrupt Clear</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_ICR_CBECINT</name>
|
|
<description>GPTM Capture B Event Interrupt Clear</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAILR</name>
|
|
<description>GPTM Timer A Interval Load</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAILR_TAILRL</name>
|
|
<description>GPTM Timer A Interval Load Register Low</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAILR_TAILRH</name>
|
|
<description>GPTM Timer A Interval Load Register High</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBILR</name>
|
|
<description>GPTM Timer B Interval Load</description>
|
|
<addressOffset>0x0000002C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBILR_TBILRL</name>
|
|
<description>GPTM Timer B Interval Load Register</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAMATCHR</name>
|
|
<description>GPTM Timer A Match</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAMATCHR_TAMRL</name>
|
|
<description>GPTM Timer A Match Register Low</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAMATCHR_TAMRH</name>
|
|
<description>GPTM Timer A Match Register High</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBMATCHR</name>
|
|
<description>GPTM Timer B Match</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBMATCHR_TBMRL</name>
|
|
<description>GPTM Timer B Match Register Low</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAPR</name>
|
|
<description>GPTM Timer A Prescale</description>
|
|
<addressOffset>0x00000038</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAPR_TAPSR</name>
|
|
<description>GPTM Timer A Prescale</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPR</name>
|
|
<description>GPTM Timer B Prescale</description>
|
|
<addressOffset>0x0000003C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBPR_TBPSR</name>
|
|
<description>GPTM Timer B Prescale</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAPMR</name>
|
|
<description>GPTM TimerA Prescale Match</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAPMR_TAPSMR</name>
|
|
<description>GPTM TimerA Prescale Match</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBPMR</name>
|
|
<description>GPTM TimerB Prescale Match</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBPMR_TBPSMR</name>
|
|
<description>GPTM TimerB Prescale Match</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TAR</name>
|
|
<description>GPTM Timer A</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TAR_TARL</name>
|
|
<description>GPTM Timer A Register Low</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>TIMER_TAR_TARH</name>
|
|
<description>GPTM Timer A Register High</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TBR</name>
|
|
<description>GPTM Timer B</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>TIMER_TBR_TBRL</name>
|
|
<description>GPTM Timer B</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER1</name>
|
|
<prependToName>TIMER1</prependToName>
|
|
<baseAddress>0x40031000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIMER0">
|
|
<name>TIMER2</name>
|
|
<prependToName>TIMER2</prependToName>
|
|
<baseAddress>0x40032000</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC0</name>
|
|
<description>Register map for ADC0 peripheral</description>
|
|
<groupName>ADC</groupName>
|
|
<prependToName>ADC0</prependToName>
|
|
<baseAddress>0x40038000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACTSS</name>
|
|
<description>ADC Active Sample Sequencer</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN0</name>
|
|
<description>ADC SS0 Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN1</name>
|
|
<description>ADC SS1 Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN2</name>
|
|
<description>ADC SS2 Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ACTSS_ASEN3</name>
|
|
<description>ADC SS3 Enable</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>ADC Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_RIS_INR0</name>
|
|
<description>SS0 Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR1</name>
|
|
<description>SS1 Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR2</name>
|
|
<description>SS2 Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_RIS_INR3</name>
|
|
<description>SS3 Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IM</name>
|
|
<description>ADC Interrupt Mask</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_IM_MASK0</name>
|
|
<description>SS0 Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK1</name>
|
|
<description>SS1 Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK2</name>
|
|
<description>SS2 Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_IM_MASK3</name>
|
|
<description>SS3 Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISC</name>
|
|
<description>ADC Interrupt Status and Clear</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_ISC_IN0</name>
|
|
<description>SS0 Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN1</name>
|
|
<description>SS1 Interrupt Status and Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN2</name>
|
|
<description>SS2 Interrupt Status and Clear</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_ISC_IN3</name>
|
|
<description>SS3 Interrupt Status and Clear</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSTAT</name>
|
|
<description>ADC Overflow Status</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_OSTAT_OV0</name>
|
|
<description>SS0 FIFO Overflow</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV1</name>
|
|
<description>SS1 FIFO Overflow</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV2</name>
|
|
<description>SS2 FIFO Overflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_OSTAT_OV3</name>
|
|
<description>SS3 FIFO Overflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMUX</name>
|
|
<description>ADC Event Multiplexer Select</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_EMUX_EM0</name>
|
|
<description>SS0 Trigger Select</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_EXTERNAL</name>
|
|
<description>External (GPIO PB4)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM0</name>
|
|
<description>PWM0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM1</name>
|
|
<description>PWM1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_PWM2</name>
|
|
<description>PWM2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM0_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM1</name>
|
|
<description>SS1 Trigger Select</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_EXTERNAL</name>
|
|
<description>External (GPIO PB4)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM0</name>
|
|
<description>PWM0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM1</name>
|
|
<description>PWM1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_PWM2</name>
|
|
<description>PWM2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM1_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM2</name>
|
|
<description>SS2 Trigger Select</description>
|
|
<bitRange>[11:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_EXTERNAL</name>
|
|
<description>External (GPIO PB4)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM0</name>
|
|
<description>PWM0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM1</name>
|
|
<description>PWM1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_PWM2</name>
|
|
<description>PWM2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM2_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_EMUX_EM3</name>
|
|
<description>SS3 Trigger Select</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PROCESSOR</name>
|
|
<description>Processor (default)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_COMP0</name>
|
|
<description>Analog Comparator 0</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_EXTERNAL</name>
|
|
<description>External (GPIO PB4)</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_TIMER</name>
|
|
<description>Timer</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM0</name>
|
|
<description>PWM0</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM1</name>
|
|
<description>PWM1</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_PWM2</name>
|
|
<description>PWM2</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_EMUX_EM3_ALWAYS</name>
|
|
<description>Always (continuously sample)</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>USTAT</name>
|
|
<description>ADC Underflow Status</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_USTAT_UV0</name>
|
|
<description>SS0 FIFO Underflow</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV1</name>
|
|
<description>SS1 FIFO Underflow</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV2</name>
|
|
<description>SS2 FIFO Underflow</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_USTAT_UV3</name>
|
|
<description>SS3 FIFO Underflow</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSPRI</name>
|
|
<description>ADC Sample Sequencer Priority</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSPRI_SS0</name>
|
|
<description>SS0 Priority</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS0_1ST</name>
|
|
<description>First priority</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS0_2ND</name>
|
|
<description>Second priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS0_3RD</name>
|
|
<description>Third priority</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS0_4TH</name>
|
|
<description>Fourth priority</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS1</name>
|
|
<description>SS1 Priority</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS1_1ST</name>
|
|
<description>First priority</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS1_2ND</name>
|
|
<description>Second priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS1_3RD</name>
|
|
<description>Third priority</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS1_4TH</name>
|
|
<description>Fourth priority</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS2</name>
|
|
<description>SS2 Priority</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS2_1ST</name>
|
|
<description>First priority</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS2_2ND</name>
|
|
<description>Second priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS2_3RD</name>
|
|
<description>Third priority</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS2_4TH</name>
|
|
<description>Fourth priority</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSPRI_SS3</name>
|
|
<description>SS3 Priority</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS3_1ST</name>
|
|
<description>First priority</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS3_2ND</name>
|
|
<description>Second priority</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS3_3RD</name>
|
|
<description>Third priority</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SSPRI_SS3_4TH</name>
|
|
<description>Fourth priority</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSSI</name>
|
|
<description>ADC Processor Sample Sequence Initiate</description>
|
|
<addressOffset>0x00000028</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_PSSI_SS0</name>
|
|
<description>SS0 Initiate</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS1</name>
|
|
<description>SS1 Initiate</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS2</name>
|
|
<description>SS2 Initiate</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_PSSI_SS3</name>
|
|
<description>SS3 Initiate</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SAC</name>
|
|
<description>ADC Sample Averaging Control</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SAC_AVG</name>
|
|
<description>Hardware Averaging Control</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_OFF</name>
|
|
<description>No hardware oversampling</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_2X</name>
|
|
<description>2x hardware oversampling</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_4X</name>
|
|
<description>4x hardware oversampling</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_8X</name>
|
|
<description>8x hardware oversampling</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_16X</name>
|
|
<description>16x hardware oversampling</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_32X</name>
|
|
<description>32x hardware oversampling</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>ADC_SAC_AVG_64X</name>
|
|
<description>64x hardware oversampling</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX0</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 0</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX4</name>
|
|
<description>5th Sample Input Select</description>
|
|
<bitRange>[17:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX5</name>
|
|
<description>6th Sample Input Select</description>
|
|
<bitRange>[21:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX6</name>
|
|
<description>7th Sample Input Select</description>
|
|
<bitRange>[25:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX0_MUX7</name>
|
|
<description>8th Sample Input Select</description>
|
|
<bitRange>[29:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL0</name>
|
|
<description>ADC Sample Sequence Control 0</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL0_D0</name>
|
|
<description>1st Sample Diff Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D1</name>
|
|
<description>2nd Sample Diff Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D2</name>
|
|
<description>3rd Sample Diff Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D3</name>
|
|
<description>4th Sample Diff Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D4</name>
|
|
<description>5th Sample Diff Input Select</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END4</name>
|
|
<description>5th Sample is End of Sequence</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE4</name>
|
|
<description>5th Sample Interrupt Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS4</name>
|
|
<description>5th Sample Temp Sensor Select</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D5</name>
|
|
<description>6th Sample Diff Input Select</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END5</name>
|
|
<description>6th Sample is End of Sequence</description>
|
|
<bitRange>[21:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE5</name>
|
|
<description>6th Sample Interrupt Enable</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS5</name>
|
|
<description>6th Sample Temp Sensor Select</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D6</name>
|
|
<description>7th Sample Diff Input Select</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END6</name>
|
|
<description>7th Sample is End of Sequence</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE6</name>
|
|
<description>7th Sample Interrupt Enable</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS6</name>
|
|
<description>7th Sample Temp Sensor Select</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_D7</name>
|
|
<description>8th Sample Diff Input Select</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_END7</name>
|
|
<description>8th Sample is End of Sequence</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_IE7</name>
|
|
<description>8th Sample Interrupt Enable</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL0_TS7</name>
|
|
<description>8th Sample Temp Sensor Select</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO0</name>
|
|
<description>ADC Sample Sequence Result FIFO 0</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO0_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT0</name>
|
|
<description>ADC Sample Sequence FIFO 0 Status</description>
|
|
<addressOffset>0x0000004C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT0_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX1</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 1</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX1_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL1</name>
|
|
<description>ADC Sample Sequence Control 1</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL1_D0</name>
|
|
<description>1st Sample Diff Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D1</name>
|
|
<description>2nd Sample Diff Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D2</name>
|
|
<description>3rd Sample Diff Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_D3</name>
|
|
<description>4th Sample Diff Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL1_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO1</name>
|
|
<description>ADC Sample Sequence Result FIFO 1</description>
|
|
<addressOffset>0x00000068</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO1_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT1</name>
|
|
<description>ADC Sample Sequence FIFO 1 Status</description>
|
|
<addressOffset>0x0000006C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT1_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX2</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 2</description>
|
|
<addressOffset>0x00000080</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX1</name>
|
|
<description>2nd Sample Input Select</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX2</name>
|
|
<description>3rd Sample Input Select</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSMUX2_MUX3</name>
|
|
<description>4th Sample Input Select</description>
|
|
<bitRange>[13:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL2</name>
|
|
<description>ADC Sample Sequence Control 2</description>
|
|
<addressOffset>0x00000084</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL2_D0</name>
|
|
<description>1st Sample Diff Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D1</name>
|
|
<description>2nd Sample Diff Input Select</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END1</name>
|
|
<description>2nd Sample is End of Sequence</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE1</name>
|
|
<description>2nd Sample Interrupt Enable</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS1</name>
|
|
<description>2nd Sample Temp Sensor Select</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D2</name>
|
|
<description>3rd Sample Diff Input Select</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END2</name>
|
|
<description>3rd Sample is End of Sequence</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE2</name>
|
|
<description>3rd Sample Interrupt Enable</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS2</name>
|
|
<description>3rd Sample Temp Sensor Select</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_D3</name>
|
|
<description>4th Sample Diff Input Select</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_END3</name>
|
|
<description>4th Sample is End of Sequence</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_IE3</name>
|
|
<description>4th Sample Interrupt Enable</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL2_TS3</name>
|
|
<description>4th Sample Temp Sensor Select</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO2</name>
|
|
<description>ADC Sample Sequence Result FIFO 2</description>
|
|
<addressOffset>0x00000088</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO2_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT2</name>
|
|
<description>ADC Sample Sequence FIFO 2 Status</description>
|
|
<addressOffset>0x0000008C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT2_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSMUX3</name>
|
|
<description>ADC Sample Sequence Input Multiplexer Select 3</description>
|
|
<addressOffset>0x000000A0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSMUX3_MUX0</name>
|
|
<description>1st Sample Input Select</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSCTL3</name>
|
|
<description>ADC Sample Sequence Control 3</description>
|
|
<addressOffset>0x000000A4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSCTL3_D0</name>
|
|
<description>1st Sample Diff Input Select</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_END0</name>
|
|
<description>1st Sample is End of Sequence</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_IE0</name>
|
|
<description>1st Sample Interrupt Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSCTL3_TS0</name>
|
|
<description>1st Sample Temp Sensor Select</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFIFO3</name>
|
|
<description>ADC Sample Sequence Result FIFO 3</description>
|
|
<addressOffset>0x000000A8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFIFO3_DATA</name>
|
|
<description>Conversion Result Data</description>
|
|
<bitRange>[9:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSFSTAT3</name>
|
|
<description>ADC Sample Sequence FIFO 3 Status</description>
|
|
<addressOffset>0x000000AC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_TPTR</name>
|
|
<description>FIFO Tail Pointer</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_HPTR</name>
|
|
<description>FIFO Head Pointer</description>
|
|
<bitRange>[7:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_EMPTY</name>
|
|
<description>FIFO Empty</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>ADC_SSFSTAT3_FULL</name>
|
|
<description>FIFO Full</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TMLB</name>
|
|
<description>ADC Test Mode Loopback</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>ADC_TMLB_LB</name>
|
|
<description>Loopback Mode Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP</name>
|
|
<description>Register map for COMP peripheral</description>
|
|
<groupName>COMP</groupName>
|
|
<prependToName>COMP</prependToName>
|
|
<baseAddress>0x4003C000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACMIS</name>
|
|
<description>Analog Comparator Masked Interrupt Status</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACMIS_IN0</name>
|
|
<description>Comparator 0 Masked Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACRIS</name>
|
|
<description>Analog Comparator Raw Interrupt Status</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACRIS_IN0</name>
|
|
<description>Comparator 0 Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACINTEN</name>
|
|
<description>Analog Comparator Interrupt Enable</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACINTEN_IN0</name>
|
|
<description>Comparator 0 Interrupt Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACREFCTL</name>
|
|
<description>Analog Comparator Reference Voltage Control</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACREFCTL_VREF</name>
|
|
<description>Resistor Ladder Voltage Ref</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACREFCTL_RNG</name>
|
|
<description>Resistor Ladder Range</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACREFCTL_EN</name>
|
|
<description>Resistor Ladder Enable</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACSTAT0</name>
|
|
<description>Analog Comparator Status 0</description>
|
|
<addressOffset>0x00000020</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACSTAT0_OVAL</name>
|
|
<description>Comparator Output Value</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACCTL0</name>
|
|
<description>Analog Comparator Control 0</description>
|
|
<addressOffset>0x00000024</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_ACCTL0_CINV</name>
|
|
<description>Comparator Output Invert</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ISEN</name>
|
|
<description>Interrupt Sense</description>
|
|
<bitRange>[3:2]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_LEVEL</name>
|
|
<description>Level sense, see ISLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ISEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ISLVAL</name>
|
|
<description>Interrupt Sense Level Value</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TSEN</name>
|
|
<description>Trigger Sense</description>
|
|
<bitRange>[6:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_LEVEL</name>
|
|
<description>Level sense, see TSLVAL</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_FALL</name>
|
|
<description>Falling edge</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_RISE</name>
|
|
<description>Rising edge</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_TSEN_BOTH</name>
|
|
<description>Either edge</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TSLVAL</name>
|
|
<description>Trigger Sense Level Value</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_ASRCP</name>
|
|
<description>Analog Source Positive</description>
|
|
<bitRange>[10:9]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_PIN</name>
|
|
<description>Pin value of Cn+</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_PIN0</name>
|
|
<description>Pin value of C0+</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>COMP_ACCTL0_ASRCP_REF</name>
|
|
<description>Internal voltage reference (VIREF)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>COMP_ACCTL0_TOEN</name>
|
|
<description>Trigger Output Enable</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASH_CTRL</name>
|
|
<description>Register map for FLASH_CTRL peripheral</description>
|
|
<groupName>FLASH_CTRL</groupName>
|
|
<prependToName>FLASH_CTRL</prependToName>
|
|
<baseAddress>0x400FD000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<addressBlock>
|
|
<offset>0x1000</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>FMA</name>
|
|
<description>Flash Memory Address</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMA_OFFSET</name>
|
|
<description>Address Offset</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMD</name>
|
|
<description>Flash Memory Data</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMD_DATA</name>
|
|
<description>Data Value</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMC</name>
|
|
<description>Flash Memory Control</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FMC_WRITE</name>
|
|
<description>Write a Word into Flash Memory</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_ERASE</name>
|
|
<description>Erase a Page of Flash Memory</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_MERASE</name>
|
|
<description>Mass Erase Flash Memory</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_COMT</name>
|
|
<description>Commit Register Value</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FMC_WRKEY</name>
|
|
<description>FLASH write key</description>
|
|
<bitRange>[31:17]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCRIS</name>
|
|
<description>Flash Controller Raw Interrupt Status</description>
|
|
<addressOffset>0x0000000C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCRIS_ARIS</name>
|
|
<description>Access Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCRIS_PRIS</name>
|
|
<description>Programming Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCIM</name>
|
|
<description>Flash Controller Interrupt Mask</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCIM_AMASK</name>
|
|
<description>Access Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCIM_PMASK</name>
|
|
<description>Programming Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCMISC</name>
|
|
<description>Flash Controller Masked Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_FCMISC_AMISC</name>
|
|
<description>Access Masked Interrupt Status and Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_FCMISC_PMISC</name>
|
|
<description>Programming Masked Interrupt Status and Clear</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FMPRE</name>
|
|
<description>Flash Memory Protection Read Enable</description>
|
|
<addressOffset>0x00001130</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>FMPPE</name>
|
|
<description>Flash Memory Protection Program Enable</description>
|
|
<addressOffset>0x00001134</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>USECRL</name>
|
|
<description>USec Reload</description>
|
|
<addressOffset>0x00001140</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_USECRL</name>
|
|
<description>Microsecond Reload Value</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCTL</name>
|
|
<description>Register map for SYSCTL peripheral</description>
|
|
<groupName>SYSCTL</groupName>
|
|
<prependToName>SYSCTL</prependToName>
|
|
<baseAddress>0x400FE000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DID0</name>
|
|
<description>Device Identification 0</description>
|
|
<addressOffset>0x00000000</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DID0_MIN</name>
|
|
<description>Minor Revision</description>
|
|
<bitRange>[7:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_0</name>
|
|
<description>Initial device, or a major revision update</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_1</name>
|
|
<description>First metal layer change</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MIN_2</name>
|
|
<description>Second metal layer change</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID0_MAJ</name>
|
|
<description>Major Revision</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVA</name>
|
|
<description>Revision A (initial device)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVB</name>
|
|
<description>Revision B (first base layer revision)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_MAJ_REVC</name>
|
|
<description>Revision C (second base layer revision)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID0_VER</name>
|
|
<description>DID0 Version</description>
|
|
<bitRange>[30:28]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID0_VER_0</name>
|
|
<description>Initial DID0 register format definition for Stellaris(R) Sandstorm-class devices</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DID1</name>
|
|
<description>Device Identification 1</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DID1_QUAL</name>
|
|
<description>Qualification Status</description>
|
|
<bitRange>[1:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_ES</name>
|
|
<description>Engineering Sample (unqualified)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_PP</name>
|
|
<description>Pilot Production (unqualified)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_QUAL_FQ</name>
|
|
<description>Fully Qualified</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_ROHS</name>
|
|
<description>RoHS-Compliance</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_PKG</name>
|
|
<description>Package Type</description>
|
|
<bitRange>[4:3]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PKG_SOIC</name>
|
|
<description>SOIC package</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PKG_QFP</name>
|
|
<description>LQFP package</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PKG_QFN</name>
|
|
<description>QFN package</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_TEMP</name>
|
|
<description>Temperature Range</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_C</name>
|
|
<description>Commercial temperature range (0C to 70C)</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_I</name>
|
|
<description>Industrial temperature range (-40C to 85C)</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_TEMP_E</name>
|
|
<description>Extended temperature range (-40C to 105C)</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_PRTNO</name>
|
|
<description>Part Number</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_PRTNO_811</name>
|
|
<description>LM3S811</description>
|
|
<value>0x32</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_FAM</name>
|
|
<description>Family</description>
|
|
<bitRange>[27:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_FAM_STELLARIS</name>
|
|
<description>Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DID1_VER</name>
|
|
<description>DID1 Version</description>
|
|
<bitRange>[31:28]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DID1_VER_0</name>
|
|
<description>Initial DID1 register format definition, indicating a Stellaris LM3Snnn device</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC0</name>
|
|
<description>Device Capabilities 0</description>
|
|
<addressOffset>0x00000008</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DC0_FLASHSZ</name>
|
|
<description>Flash Size</description>
|
|
<bitRange>[15:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DC0_FLASHSZ_64KB</name>
|
|
<description>64 KB of Flash</description>
|
|
<value>0x1f</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC0_SRAMSZ</name>
|
|
<description>SRAM Size</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DC0_SRAMSZ_8KB</name>
|
|
<description>8 KB of SRAM</description>
|
|
<value>0x1f</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC1</name>
|
|
<description>Device Capabilities 1</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DC1_JTAG</name>
|
|
<description>JTAG Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_SWD</name>
|
|
<description>SWD Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_SWO</name>
|
|
<description>SWO Trace Port Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_WDT0</name>
|
|
<description>Watchdog Timer 0 Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_PLL</name>
|
|
<description>PLL Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_TEMP</name>
|
|
<description>Temp Sensor Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_MPU</name>
|
|
<description>MPU Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC1_MINSYSDIV</name>
|
|
<description>System Clock Divider</description>
|
|
<bitRange>[15:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_DC1_MINSYSDIV_50</name>
|
|
<description>Specifies a 50-MHz CPU clock with a PLL divider of 4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC2</name>
|
|
<description>Device Capabilities 2</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DC2_UART0</name>
|
|
<description>UART Module 0 Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_UART1</name>
|
|
<description>UART Module 1 Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_SSI0</name>
|
|
<description>SSI Module 0 Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_I2C0</name>
|
|
<description>I2C Module 0 Present</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_TIMER0</name>
|
|
<description>Timer Module 0 Present</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_TIMER1</name>
|
|
<description>Timer Module 1 Present</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_TIMER2</name>
|
|
<description>Timer Module 2 Present</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC2_COMP0</name>
|
|
<description>Analog Comparator 0 Present</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC3</name>
|
|
<description>Device Capabilities 3</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM0</name>
|
|
<description>PWM0 Pin Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM1</name>
|
|
<description>PWM1 Pin Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM2</name>
|
|
<description>PWM2 Pin Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM3</name>
|
|
<description>PWM3 Pin Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM4</name>
|
|
<description>PWM4 Pin Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_PWM5</name>
|
|
<description>PWM5 Pin Present</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_C0MINUS</name>
|
|
<description>C0- Pin Present</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_C0PLUS</name>
|
|
<description>C0+ Pin Present</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_C0O</name>
|
|
<description>C0o Pin Present</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP0</name>
|
|
<description>CCP0 Pin Present</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP1</name>
|
|
<description>CCP1 Pin Present</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP2</name>
|
|
<description>CCP2 Pin Present</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP3</name>
|
|
<description>CCP3 Pin Present</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP4</name>
|
|
<description>CCP4 Pin Present</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_CCP5</name>
|
|
<description>CCP5 Pin Present</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC3_32KHZ</name>
|
|
<description>32KHz Input Clock Available</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DC4</name>
|
|
<description>Device Capabilities 4</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DC4_GPIOA</name>
|
|
<description>GPIO Port A Present</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC4_GPIOB</name>
|
|
<description>GPIO Port B Present</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC4_GPIOC</name>
|
|
<description>GPIO Port C Present</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC4_GPIOD</name>
|
|
<description>GPIO Port D Present</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DC4_GPIOE</name>
|
|
<description>GPIO Port E Present</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBORCTL</name>
|
|
<description>Brown-Out Reset Control</description>
|
|
<addressOffset>0x00000030</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PBORCTL_BORWT</name>
|
|
<description>BOR Wait and Check for Noise</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PBORCTL_BORIOR</name>
|
|
<description>BOR Interrupt or Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PBORCTL_BORTIM</name>
|
|
<description>BOR Time Delay</description>
|
|
<bitRange>[15:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDOPCTL</name>
|
|
<description>LDO Power Control</description>
|
|
<addressOffset>0x00000034</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_LDOPCTL</name>
|
|
<description>LDO Output Voltage</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_50V</name>
|
|
<description>2.50</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_45V</name>
|
|
<description>2.45</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_40V</name>
|
|
<description>2.40</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_35V</name>
|
|
<description>2.35</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_30V</name>
|
|
<description>2.30</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_25V</name>
|
|
<description>2.25</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_75V</name>
|
|
<description>2.75</description>
|
|
<value>0x1b</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_70V</name>
|
|
<description>2.70</description>
|
|
<value>0x1c</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_65V</name>
|
|
<description>2.65</description>
|
|
<value>0x1d</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_60V</name>
|
|
<description>2.60</description>
|
|
<value>0x1e</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_LDOPCTL_2_55V</name>
|
|
<description>2.55</description>
|
|
<value>0x1f</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCR0</name>
|
|
<description>Software Reset Control 0</description>
|
|
<addressOffset>0x00000040</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>SRCR1</name>
|
|
<description>Software Reset Control 1</description>
|
|
<addressOffset>0x00000044</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_UART0</name>
|
|
<description>UART0 Reset Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_UART1</name>
|
|
<description>UART1 Reset Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_SSI0</name>
|
|
<description>SSI0 Reset Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_I2C0</name>
|
|
<description>I2C0 Reset Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_TIMER0</name>
|
|
<description>Timer 0 Reset Control</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_TIMER1</name>
|
|
<description>Timer 1 Reset Control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_TIMER2</name>
|
|
<description>Timer 2 Reset Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR1_COMP0</name>
|
|
<description>Analog Comp 0 Reset Control</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SRCR2</name>
|
|
<description>Software Reset Control 2</description>
|
|
<addressOffset>0x00000048</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SRCR2_GPIOA</name>
|
|
<description>Port A Reset Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR2_GPIOB</name>
|
|
<description>Port B Reset Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR2_GPIOC</name>
|
|
<description>Port C Reset Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR2_GPIOD</name>
|
|
<description>Port D Reset Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SRCR2_GPIOE</name>
|
|
<description>Port E Reset Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RIS</name>
|
|
<description>Raw Interrupt Status</description>
|
|
<addressOffset>0x00000050</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RIS_PLLFRIS</name>
|
|
<description>PLL Fault Raw Interrupt Status</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_BORRIS</name>
|
|
<description>Brown-Out Reset Raw Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_LDORIS</name>
|
|
<description>LDO Power Unregulated Raw Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_MOFRIS</name>
|
|
<description>Main Oscillator Fault Raw Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_IOFRIS</name>
|
|
<description>Internal Oscillator Fault Raw Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_CLRIS</name>
|
|
<description>Current Limit Raw Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RIS_PLLLRIS</name>
|
|
<description>PLL Lock Raw Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMC</name>
|
|
<description>Interrupt Mask Control</description>
|
|
<addressOffset>0x00000054</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_IMC_PLLFIM</name>
|
|
<description>PLL Fault Interrupt Mask</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_BORIM</name>
|
|
<description>Brown-Out Reset Interrupt Mask</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_LDOIM</name>
|
|
<description>LDO Power Unregulated Interrupt Mask</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_MOFIM</name>
|
|
<description>Main Oscillator Fault Interrupt Mask</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_IOFIM</name>
|
|
<description>Internal Oscillator Fault Interrupt Mask</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_CLIM</name>
|
|
<description>Current Limit Interrupt Mask</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_IMC_PLLLIM</name>
|
|
<description>PLL Lock Interrupt Mask</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISC</name>
|
|
<description>Masked Interrupt Status and Clear</description>
|
|
<addressOffset>0x00000058</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_MISC_BORMIS</name>
|
|
<description>BOR Masked Interrupt Status</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_LDOMIS</name>
|
|
<description>LDO Power Unregulated Masked Interrupt Status</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_MOFMIS</name>
|
|
<description>Main Oscillator Fault Masked Interrupt Status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_IOFMIS</name>
|
|
<description>Internal Oscillator Fault Masked Interrupt Status</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_CLMIS</name>
|
|
<description>Current Limit Masked Interrupt Status</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_MISC_PLLLMIS</name>
|
|
<description>PLL Lock Masked Interrupt Status</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RESC</name>
|
|
<description>Reset Cause</description>
|
|
<addressOffset>0x0000005C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RESC_EXT</name>
|
|
<description>External Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_POR</name>
|
|
<description>Power-On Reset</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_BOR</name>
|
|
<description>Brown-Out Reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_SW</name>
|
|
<description>Software Reset</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RESC_LDO</name>
|
|
<description>LDO Reset</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCC</name>
|
|
<description>Run-Mode Clock Configuration</description>
|
|
<addressOffset>0x00000060</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCC_MOSCDIS</name>
|
|
<description>Main Oscillator Disable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_IOSCDIS</name>
|
|
<description>Internal Oscillator Disable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_MOSCVER</name>
|
|
<description>Main Oscillator Verification Timer</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_IOSCVER</name>
|
|
<description>Internal Oscillator Verification Timer</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_OSCSRC</name>
|
|
<description>Oscillator Source</description>
|
|
<bitRange>[5:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_OSCSRC_MAIN</name>
|
|
<description>MOSC</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_OSCSRC_INT</name>
|
|
<description>IOSC</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_OSCSRC_INT4</name>
|
|
<description>IOSC/4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_XTAL</name>
|
|
<description>Crystal Value</description>
|
|
<bitRange>[9:6]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_1MHZ</name>
|
|
<description>1 MHz</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_1_84MHZ</name>
|
|
<description>1.8432 MHz</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_2MHZ</name>
|
|
<description>2 MHz</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_2_45MHZ</name>
|
|
<description>2.4576 MHz</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_3_57MHZ</name>
|
|
<description>3.579545 MHz</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_3_68MHZ</name>
|
|
<description>3.6864 MHz</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_4MHZ</name>
|
|
<description>4 MHz</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_4_09MHZ</name>
|
|
<description>4.096 MHz</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_4_91MHZ</name>
|
|
<description>4.9152 MHz</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_5MHZ</name>
|
|
<description>5 MHz</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_5_12MHZ</name>
|
|
<description>5.12 MHz</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_6MHZ</name>
|
|
<description>6 MHz</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_6_14MHZ</name>
|
|
<description>6.144 MHz</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_7_37MHZ</name>
|
|
<description>7.3728 MHz</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_8MHZ</name>
|
|
<description>8 MHz</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_XTAL_8_19MHZ</name>
|
|
<description>8.192 MHz</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_PLLVER</name>
|
|
<description>PLL Verification</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_BYPASS</name>
|
|
<description>PLL Bypass</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_OEN</name>
|
|
<description>PLL Output Enable</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_PWRDN</name>
|
|
<description>PLL Power Down</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_PWMDIV</name>
|
|
<description>PWM Unit Clock Divisor</description>
|
|
<bitRange>[19:17]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_2</name>
|
|
<description>PWM clock /2</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_4</name>
|
|
<description>PWM clock /4</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_8</name>
|
|
<description>PWM clock /8</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_16</name>
|
|
<description>PWM clock /16</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_32</name>
|
|
<description>PWM clock /32</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_PWMDIV_64</name>
|
|
<description>PWM clock /64</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_USEPWMDIV</name>
|
|
<description>Enable PWM Clock Divisor</description>
|
|
<bitRange>[20:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_USESYSDIV</name>
|
|
<description>Enable System Clock Divider</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_SYSDIV</name>
|
|
<description>System Clock Divisor</description>
|
|
<bitRange>[26:23]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_2</name>
|
|
<description>System clock /2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_3</name>
|
|
<description>System clock /3</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_4</name>
|
|
<description>System clock /4</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_5</name>
|
|
<description>System clock /5</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_6</name>
|
|
<description>System clock /6</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_7</name>
|
|
<description>System clock /7</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_8</name>
|
|
<description>System clock /8</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_9</name>
|
|
<description>System clock /9</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_10</name>
|
|
<description>System clock /10</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_11</name>
|
|
<description>System clock /11</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_12</name>
|
|
<description>System clock /12</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_13</name>
|
|
<description>System clock /13</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_14</name>
|
|
<description>System clock /14</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_15</name>
|
|
<description>System clock /15</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCC_SYSDIV_16</name>
|
|
<description>System clock /16</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCC_ACG</name>
|
|
<description>Auto Clock Gating</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLCFG</name>
|
|
<description>XTAL to PLL Translation</description>
|
|
<addressOffset>0x00000064</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_PLLCFG_R</name>
|
|
<description>PLL R Value</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PLLCFG_F</name>
|
|
<description>PLL F Value</description>
|
|
<bitRange>[13:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_PLLCFG_OD</name>
|
|
<description>PLL OD Value</description>
|
|
<bitRange>[15:14]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PLLCFG_OD_1</name>
|
|
<description>Divide by 1</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PLLCFG_OD_2</name>
|
|
<description>Divide by 2</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_PLLCFG_OD_4</name>
|
|
<description>Divide by 4</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGC0</name>
|
|
<description>Run Mode Clock Gating Control Register 0</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGC0_ADCSPD</name>
|
|
<description>ADC Sample Speed</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCGC0_ADCSPD125K</name>
|
|
<description>125K samples/second</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCGC0_ADCSPD250K</name>
|
|
<description>250K samples/second</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_RCGC0_ADCSPD500K</name>
|
|
<description>500K samples/second</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGC1</name>
|
|
<description>Run Mode Clock Gating Control Register 1</description>
|
|
<addressOffset>0x00000104</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_UART0</name>
|
|
<description>UART0 Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_UART1</name>
|
|
<description>UART1 Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_SSI0</name>
|
|
<description>SSI0 Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_I2C0</name>
|
|
<description>I2C0 Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_TIMER0</name>
|
|
<description>Timer 0 Clock Gating Control</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_TIMER1</name>
|
|
<description>Timer 1 Clock Gating Control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_TIMER2</name>
|
|
<description>Timer 2 Clock Gating Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC1_COMP0</name>
|
|
<description>Analog Comparator 0 Clock Gating</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCGC2</name>
|
|
<description>Run Mode Clock Gating Control Register 2</description>
|
|
<addressOffset>0x00000108</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_RCGC2_GPIOA</name>
|
|
<description>Port A Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC2_GPIOB</name>
|
|
<description>Port B Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC2_GPIOC</name>
|
|
<description>Port C Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC2_GPIOD</name>
|
|
<description>Port D Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_RCGC2_GPIOE</name>
|
|
<description>Port E Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC0</name>
|
|
<description>Sleep Mode Clock Gating Control Register 0</description>
|
|
<addressOffset>0x00000110</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGC0_ADCSPD</name>
|
|
<description>ADC Sample Speed</description>
|
|
<bitRange>[9:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SCGC0_ADCSPD125K</name>
|
|
<description>125K samples/second</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SCGC0_ADCSPD250K</name>
|
|
<description>250K samples/second</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>SYSCTL_SCGC0_ADCSPD500K</name>
|
|
<description>500K samples/second</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC1</name>
|
|
<description>Sleep Mode Clock Gating Control Register 1</description>
|
|
<addressOffset>0x00000114</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_UART0</name>
|
|
<description>UART0 Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_UART1</name>
|
|
<description>UART1 Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_SSI0</name>
|
|
<description>SSI0 Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_I2C0</name>
|
|
<description>I2C0 Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_TIMER0</name>
|
|
<description>Timer 0 Clock Gating Control</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_TIMER1</name>
|
|
<description>Timer 1 Clock Gating Control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_TIMER2</name>
|
|
<description>Timer 2 Clock Gating Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC1_COMP0</name>
|
|
<description>Analog Comparator 0 Clock Gating</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCGC2</name>
|
|
<description>Sleep Mode Clock Gating Control Register 2</description>
|
|
<addressOffset>0x00000118</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_SCGC2_GPIOA</name>
|
|
<description>Port A Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC2_GPIOB</name>
|
|
<description>Port B Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC2_GPIOC</name>
|
|
<description>Port C Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC2_GPIOD</name>
|
|
<description>Port D Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_SCGC2_GPIOE</name>
|
|
<description>Port E Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGC0</name>
|
|
<description>Deep Sleep Mode Clock Gating Control Register 0</description>
|
|
<addressOffset>0x00000120</addressOffset>
|
|
</register>
|
|
<register>
|
|
<name>DCGC1</name>
|
|
<description>Deep-Sleep Mode Clock Gating Control Register 1</description>
|
|
<addressOffset>0x00000124</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_UART0</name>
|
|
<description>UART0 Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_UART1</name>
|
|
<description>UART1 Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_SSI0</name>
|
|
<description>SSI0 Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_I2C0</name>
|
|
<description>I2C0 Clock Gating Control</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_TIMER0</name>
|
|
<description>Timer 0 Clock Gating Control</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_TIMER1</name>
|
|
<description>Timer 1 Clock Gating Control</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_TIMER2</name>
|
|
<description>Timer 2 Clock Gating Control</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC1_COMP0</name>
|
|
<description>Analog Comparator 0 Clock Gating</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCGC2</name>
|
|
<description>Deep Sleep Mode Clock Gating Control Register 2</description>
|
|
<addressOffset>0x00000128</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DCGC2_GPIOA</name>
|
|
<description>Port A Clock Gating Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC2_GPIOB</name>
|
|
<description>Port B Clock Gating Control</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC2_GPIOC</name>
|
|
<description>Port C Clock Gating Control</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC2_GPIOD</name>
|
|
<description>Port D Clock Gating Control</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>SYSCTL_DCGC2_GPIOE</name>
|
|
<description>Port E Clock Gating Control</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DSLPCLKCFG</name>
|
|
<description>Deep Sleep Clock Configuration</description>
|
|
<addressOffset>0x00000144</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_DSLPCLKCFG_IOSC</name>
|
|
<description>IOSC Clock Source</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CLKVCLR</name>
|
|
<description>Clock Verification Clear</description>
|
|
<addressOffset>0x00000150</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_CLKVCLR_VERCLR</name>
|
|
<description>Clock Verification Clear</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LDOARST</name>
|
|
<description>Allow Unregulated LDO to Reset the Part</description>
|
|
<addressOffset>0x00000160</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCTL_LDOARST_LDOARST</name>
|
|
<description>LDO Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Register map for NVIC peripheral</description>
|
|
<groupName>NVIC</groupName>
|
|
<prependToName>NVIC</prependToName>
|
|
<baseAddress>0xE000E000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00001000</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>INT_TYPE</name>
|
|
<description>Interrupt Controller Type Reg</description>
|
|
<addressOffset>0x00000004</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_INT_TYPE_LINES</name>
|
|
<description>Number of interrupt lines (x32)</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST_CTRL</name>
|
|
<description>SysTick Control and Status Register</description>
|
|
<addressOffset>0x00000010</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_ST_CTRL_ENABLE</name>
|
|
<description>Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_ST_CTRL_INTEN</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_ST_CTRL_CLK_SRC</name>
|
|
<description>Clock Source</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_ST_CTRL_COUNT</name>
|
|
<description>Count Flag</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST_RELOAD</name>
|
|
<description>SysTick Reload Value Register</description>
|
|
<addressOffset>0x00000014</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_ST_RELOAD</name>
|
|
<description>Reload Value</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST_CURRENT</name>
|
|
<description>SysTick Current Value Register</description>
|
|
<addressOffset>0x00000018</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_ST_CURRENT</name>
|
|
<description>Current Value</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ST_CAL</name>
|
|
<description>SysTick Calibration Value Reg</description>
|
|
<addressOffset>0x0000001C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_ST_CAL_ONEMS</name>
|
|
<description>1ms reference value</description>
|
|
<bitRange>[23:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_ST_CAL_SKEW</name>
|
|
<description>Clock skew</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_ST_CAL_NOREF</name>
|
|
<description>No reference clock</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EN0</name>
|
|
<description>Interrupt 0-31 Set Enable</description>
|
|
<addressOffset>0x00000100</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_EN0_INT</name>
|
|
<description>Interrupt Enable</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT0</name>
|
|
<description>Interrupt 0 enable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT1</name>
|
|
<description>Interrupt 1 enable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT2</name>
|
|
<description>Interrupt 2 enable</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT3</name>
|
|
<description>Interrupt 3 enable</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT4</name>
|
|
<description>Interrupt 4 enable</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT5</name>
|
|
<description>Interrupt 5 enable</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT6</name>
|
|
<description>Interrupt 6 enable</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT7</name>
|
|
<description>Interrupt 7 enable</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT8</name>
|
|
<description>Interrupt 8 enable</description>
|
|
<value>0x100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT9</name>
|
|
<description>Interrupt 9 enable</description>
|
|
<value>0x200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT10</name>
|
|
<description>Interrupt 10 enable</description>
|
|
<value>0x400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT11</name>
|
|
<description>Interrupt 11 enable</description>
|
|
<value>0x800</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT12</name>
|
|
<description>Interrupt 12 enable</description>
|
|
<value>0x1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT13</name>
|
|
<description>Interrupt 13 enable</description>
|
|
<value>0x2000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT14</name>
|
|
<description>Interrupt 14 enable</description>
|
|
<value>0x4000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT15</name>
|
|
<description>Interrupt 15 enable</description>
|
|
<value>0x8000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT16</name>
|
|
<description>Interrupt 16 enable</description>
|
|
<value>0x10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT17</name>
|
|
<description>Interrupt 17 enable</description>
|
|
<value>0x20000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT18</name>
|
|
<description>Interrupt 18 enable</description>
|
|
<value>0x40000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT19</name>
|
|
<description>Interrupt 19 enable</description>
|
|
<value>0x80000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT20</name>
|
|
<description>Interrupt 20 enable</description>
|
|
<value>0x100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT21</name>
|
|
<description>Interrupt 21 enable</description>
|
|
<value>0x200000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT22</name>
|
|
<description>Interrupt 22 enable</description>
|
|
<value>0x400000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT23</name>
|
|
<description>Interrupt 23 enable</description>
|
|
<value>0x800000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT24</name>
|
|
<description>Interrupt 24 enable</description>
|
|
<value>0x1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT25</name>
|
|
<description>Interrupt 25 enable</description>
|
|
<value>0x2000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT26</name>
|
|
<description>Interrupt 26 enable</description>
|
|
<value>0x4000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT27</name>
|
|
<description>Interrupt 27 enable</description>
|
|
<value>0x8000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT28</name>
|
|
<description>Interrupt 28 enable</description>
|
|
<value>0x10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_EN0_INT29</name>
|
|
<description>Interrupt 29 enable</description>
|
|
<value>0x20000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIS0</name>
|
|
<description>Interrupt 0-31 Clear Enable</description>
|
|
<addressOffset>0x00000180</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DIS0_INT</name>
|
|
<description>Interrupt Disable</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT0</name>
|
|
<description>Interrupt 0 disable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT1</name>
|
|
<description>Interrupt 1 disable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT2</name>
|
|
<description>Interrupt 2 disable</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT3</name>
|
|
<description>Interrupt 3 disable</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT4</name>
|
|
<description>Interrupt 4 disable</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT5</name>
|
|
<description>Interrupt 5 disable</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT6</name>
|
|
<description>Interrupt 6 disable</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT7</name>
|
|
<description>Interrupt 7 disable</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT8</name>
|
|
<description>Interrupt 8 disable</description>
|
|
<value>0x100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT9</name>
|
|
<description>Interrupt 9 disable</description>
|
|
<value>0x200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT10</name>
|
|
<description>Interrupt 10 disable</description>
|
|
<value>0x400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT11</name>
|
|
<description>Interrupt 11 disable</description>
|
|
<value>0x800</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT12</name>
|
|
<description>Interrupt 12 disable</description>
|
|
<value>0x1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT13</name>
|
|
<description>Interrupt 13 disable</description>
|
|
<value>0x2000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT14</name>
|
|
<description>Interrupt 14 disable</description>
|
|
<value>0x4000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT15</name>
|
|
<description>Interrupt 15 disable</description>
|
|
<value>0x8000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT16</name>
|
|
<description>Interrupt 16 disable</description>
|
|
<value>0x10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT17</name>
|
|
<description>Interrupt 17 disable</description>
|
|
<value>0x20000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT18</name>
|
|
<description>Interrupt 18 disable</description>
|
|
<value>0x40000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT19</name>
|
|
<description>Interrupt 19 disable</description>
|
|
<value>0x80000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT20</name>
|
|
<description>Interrupt 20 disable</description>
|
|
<value>0x100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT21</name>
|
|
<description>Interrupt 21 disable</description>
|
|
<value>0x200000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT22</name>
|
|
<description>Interrupt 22 disable</description>
|
|
<value>0x400000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT23</name>
|
|
<description>Interrupt 23 disable</description>
|
|
<value>0x800000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT24</name>
|
|
<description>Interrupt 24 disable</description>
|
|
<value>0x1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT25</name>
|
|
<description>Interrupt 25 disable</description>
|
|
<value>0x2000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT26</name>
|
|
<description>Interrupt 26 disable</description>
|
|
<value>0x4000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT27</name>
|
|
<description>Interrupt 27 disable</description>
|
|
<value>0x8000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT28</name>
|
|
<description>Interrupt 28 disable</description>
|
|
<value>0x10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DIS0_INT29</name>
|
|
<description>Interrupt 29 disable</description>
|
|
<value>0x20000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PEND0</name>
|
|
<description>Interrupt 0-31 Set Pending</description>
|
|
<addressOffset>0x00000200</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PEND0_INT</name>
|
|
<description>Interrupt Set Pending</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT0</name>
|
|
<description>Interrupt 0 pend</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT1</name>
|
|
<description>Interrupt 1 pend</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT2</name>
|
|
<description>Interrupt 2 pend</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT3</name>
|
|
<description>Interrupt 3 pend</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT4</name>
|
|
<description>Interrupt 4 pend</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT5</name>
|
|
<description>Interrupt 5 pend</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT6</name>
|
|
<description>Interrupt 6 pend</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT7</name>
|
|
<description>Interrupt 7 pend</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT8</name>
|
|
<description>Interrupt 8 pend</description>
|
|
<value>0x100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT9</name>
|
|
<description>Interrupt 9 pend</description>
|
|
<value>0x200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT10</name>
|
|
<description>Interrupt 10 pend</description>
|
|
<value>0x400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT11</name>
|
|
<description>Interrupt 11 pend</description>
|
|
<value>0x800</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT12</name>
|
|
<description>Interrupt 12 pend</description>
|
|
<value>0x1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT13</name>
|
|
<description>Interrupt 13 pend</description>
|
|
<value>0x2000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT14</name>
|
|
<description>Interrupt 14 pend</description>
|
|
<value>0x4000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT15</name>
|
|
<description>Interrupt 15 pend</description>
|
|
<value>0x8000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT16</name>
|
|
<description>Interrupt 16 pend</description>
|
|
<value>0x10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT17</name>
|
|
<description>Interrupt 17 pend</description>
|
|
<value>0x20000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT18</name>
|
|
<description>Interrupt 18 pend</description>
|
|
<value>0x40000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT19</name>
|
|
<description>Interrupt 19 pend</description>
|
|
<value>0x80000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT20</name>
|
|
<description>Interrupt 20 pend</description>
|
|
<value>0x100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT21</name>
|
|
<description>Interrupt 21 pend</description>
|
|
<value>0x200000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT22</name>
|
|
<description>Interrupt 22 pend</description>
|
|
<value>0x400000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT23</name>
|
|
<description>Interrupt 23 pend</description>
|
|
<value>0x800000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT24</name>
|
|
<description>Interrupt 24 pend</description>
|
|
<value>0x1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT25</name>
|
|
<description>Interrupt 25 pend</description>
|
|
<value>0x2000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT26</name>
|
|
<description>Interrupt 26 pend</description>
|
|
<value>0x4000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT27</name>
|
|
<description>Interrupt 27 pend</description>
|
|
<value>0x8000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT28</name>
|
|
<description>Interrupt 28 pend</description>
|
|
<value>0x10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_PEND0_INT29</name>
|
|
<description>Interrupt 29 pend</description>
|
|
<value>0x20000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>UNPEND0</name>
|
|
<description>Interrupt 0-31 Clear Pending</description>
|
|
<addressOffset>0x00000280</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_UNPEND0_INT</name>
|
|
<description>Interrupt Clear Pending</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT0</name>
|
|
<description>Interrupt 0 unpend</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT1</name>
|
|
<description>Interrupt 1 unpend</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT2</name>
|
|
<description>Interrupt 2 unpend</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT3</name>
|
|
<description>Interrupt 3 unpend</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT4</name>
|
|
<description>Interrupt 4 unpend</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT5</name>
|
|
<description>Interrupt 5 unpend</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT6</name>
|
|
<description>Interrupt 6 unpend</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT7</name>
|
|
<description>Interrupt 7 unpend</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT8</name>
|
|
<description>Interrupt 8 unpend</description>
|
|
<value>0x100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT9</name>
|
|
<description>Interrupt 9 unpend</description>
|
|
<value>0x200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT10</name>
|
|
<description>Interrupt 10 unpend</description>
|
|
<value>0x400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT11</name>
|
|
<description>Interrupt 11 unpend</description>
|
|
<value>0x800</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT12</name>
|
|
<description>Interrupt 12 unpend</description>
|
|
<value>0x1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT13</name>
|
|
<description>Interrupt 13 unpend</description>
|
|
<value>0x2000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT14</name>
|
|
<description>Interrupt 14 unpend</description>
|
|
<value>0x4000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT15</name>
|
|
<description>Interrupt 15 unpend</description>
|
|
<value>0x8000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT16</name>
|
|
<description>Interrupt 16 unpend</description>
|
|
<value>0x10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT17</name>
|
|
<description>Interrupt 17 unpend</description>
|
|
<value>0x20000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT18</name>
|
|
<description>Interrupt 18 unpend</description>
|
|
<value>0x40000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT19</name>
|
|
<description>Interrupt 19 unpend</description>
|
|
<value>0x80000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT20</name>
|
|
<description>Interrupt 20 unpend</description>
|
|
<value>0x100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT21</name>
|
|
<description>Interrupt 21 unpend</description>
|
|
<value>0x200000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT22</name>
|
|
<description>Interrupt 22 unpend</description>
|
|
<value>0x400000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT23</name>
|
|
<description>Interrupt 23 unpend</description>
|
|
<value>0x800000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT24</name>
|
|
<description>Interrupt 24 unpend</description>
|
|
<value>0x1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT25</name>
|
|
<description>Interrupt 25 unpend</description>
|
|
<value>0x2000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT26</name>
|
|
<description>Interrupt 26 unpend</description>
|
|
<value>0x4000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT27</name>
|
|
<description>Interrupt 27 unpend</description>
|
|
<value>0x8000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT28</name>
|
|
<description>Interrupt 28 unpend</description>
|
|
<value>0x10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_UNPEND0_INT29</name>
|
|
<description>Interrupt 29 unpend</description>
|
|
<value>0x20000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACTIVE0</name>
|
|
<description>Interrupt 0-31 Active Bit</description>
|
|
<addressOffset>0x00000300</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_ACTIVE0_INT</name>
|
|
<description>Interrupt Active</description>
|
|
<bitRange>[29:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT0</name>
|
|
<description>Interrupt 0 active</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT1</name>
|
|
<description>Interrupt 1 active</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT2</name>
|
|
<description>Interrupt 2 active</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT3</name>
|
|
<description>Interrupt 3 active</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT4</name>
|
|
<description>Interrupt 4 active</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT5</name>
|
|
<description>Interrupt 5 active</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT6</name>
|
|
<description>Interrupt 6 active</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT7</name>
|
|
<description>Interrupt 7 active</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT8</name>
|
|
<description>Interrupt 8 active</description>
|
|
<value>0x100</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT9</name>
|
|
<description>Interrupt 9 active</description>
|
|
<value>0x200</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT10</name>
|
|
<description>Interrupt 10 active</description>
|
|
<value>0x400</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT11</name>
|
|
<description>Interrupt 11 active</description>
|
|
<value>0x800</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT12</name>
|
|
<description>Interrupt 12 active</description>
|
|
<value>0x1000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT13</name>
|
|
<description>Interrupt 13 active</description>
|
|
<value>0x2000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT14</name>
|
|
<description>Interrupt 14 active</description>
|
|
<value>0x4000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT15</name>
|
|
<description>Interrupt 15 active</description>
|
|
<value>0x8000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT16</name>
|
|
<description>Interrupt 16 active</description>
|
|
<value>0x10000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT17</name>
|
|
<description>Interrupt 17 active</description>
|
|
<value>0x20000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT18</name>
|
|
<description>Interrupt 18 active</description>
|
|
<value>0x40000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT19</name>
|
|
<description>Interrupt 19 active</description>
|
|
<value>0x80000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT20</name>
|
|
<description>Interrupt 20 active</description>
|
|
<value>0x100000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT21</name>
|
|
<description>Interrupt 21 active</description>
|
|
<value>0x200000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT22</name>
|
|
<description>Interrupt 22 active</description>
|
|
<value>0x400000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT23</name>
|
|
<description>Interrupt 23 active</description>
|
|
<value>0x800000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT24</name>
|
|
<description>Interrupt 24 active</description>
|
|
<value>0x1000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT25</name>
|
|
<description>Interrupt 25 active</description>
|
|
<value>0x2000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT26</name>
|
|
<description>Interrupt 26 active</description>
|
|
<value>0x4000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT27</name>
|
|
<description>Interrupt 27 active</description>
|
|
<value>0x8000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT28</name>
|
|
<description>Interrupt 28 active</description>
|
|
<value>0x10000000</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_ACTIVE0_INT29</name>
|
|
<description>Interrupt 29 active</description>
|
|
<value>0x20000000</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI0</name>
|
|
<description>Interrupt 0-3 Priority</description>
|
|
<addressOffset>0x00000400</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI0_INT0</name>
|
|
<description>Interrupt 0 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI0_INT1</name>
|
|
<description>Interrupt 1 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI0_INT2</name>
|
|
<description>Interrupt 2 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI0_INT3</name>
|
|
<description>Interrupt 3 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI1</name>
|
|
<description>Interrupt 4-7 Priority</description>
|
|
<addressOffset>0x00000404</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI1_INT4</name>
|
|
<description>Interrupt 4 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI1_INT5</name>
|
|
<description>Interrupt 5 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI1_INT6</name>
|
|
<description>Interrupt 6 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI1_INT7</name>
|
|
<description>Interrupt 7 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI2</name>
|
|
<description>Interrupt 8-11 Priority</description>
|
|
<addressOffset>0x00000408</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI2_INT8</name>
|
|
<description>Interrupt 8 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI2_INT9</name>
|
|
<description>Interrupt 9 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI2_INT10</name>
|
|
<description>Interrupt 10 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI2_INT11</name>
|
|
<description>Interrupt 11 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI3</name>
|
|
<description>Interrupt 12-15 Priority</description>
|
|
<addressOffset>0x0000040C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI3_INT12</name>
|
|
<description>Interrupt 12 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI3_INT13</name>
|
|
<description>Interrupt 13 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI3_INT14</name>
|
|
<description>Interrupt 14 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI3_INT15</name>
|
|
<description>Interrupt 15 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI4</name>
|
|
<description>Interrupt 16-19 Priority</description>
|
|
<addressOffset>0x00000410</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI4_INT16</name>
|
|
<description>Interrupt 16 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI4_INT17</name>
|
|
<description>Interrupt 17 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI4_INT18</name>
|
|
<description>Interrupt 18 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI4_INT19</name>
|
|
<description>Interrupt 19 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI5</name>
|
|
<description>Interrupt 20-23 Priority</description>
|
|
<addressOffset>0x00000414</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI5_INT20</name>
|
|
<description>Interrupt 20 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI5_INT21</name>
|
|
<description>Interrupt 21 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI5_INT22</name>
|
|
<description>Interrupt 22 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI5_INT23</name>
|
|
<description>Interrupt 23 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI6</name>
|
|
<description>Interrupt 24-27 Priority</description>
|
|
<addressOffset>0x00000418</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI6_INT24</name>
|
|
<description>Interrupt 24 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI6_INT25</name>
|
|
<description>Interrupt 25 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI6_INT26</name>
|
|
<description>Interrupt 26 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI6_INT27</name>
|
|
<description>Interrupt 27 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRI7</name>
|
|
<description>Interrupt 28-31 Priority</description>
|
|
<addressOffset>0x0000041C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_PRI7_INT28</name>
|
|
<description>Interrupt 28 Priority Mask</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI7_INT29</name>
|
|
<description>Interrupt 29 Priority Mask</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI7_INT30</name>
|
|
<description>Interrupt 30 Priority Mask</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_PRI7_INT31</name>
|
|
<description>Interrupt 31 Priority Mask</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<description>CPU ID Base</description>
|
|
<addressOffset>0x00000D00</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_CPUID_REV</name>
|
|
<description>Revision Number</description>
|
|
<bitRange>[3:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CPUID_PARTNO</name>
|
|
<description>Part Number</description>
|
|
<bitRange>[15:4]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_CPUID_PARTNO_CM3</name>
|
|
<description>Cortex-M3 processor</description>
|
|
<value>0xc23</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CPUID_CON</name>
|
|
<description>Constant</description>
|
|
<bitRange>[19:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CPUID_VAR</name>
|
|
<description>Variant Number</description>
|
|
<bitRange>[23:20]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CPUID_IMP</name>
|
|
<description>Implementer Code</description>
|
|
<bitRange>[31:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_CPUID_IMP_ARM</name>
|
|
<description>ARM</description>
|
|
<value>0x41</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INT_CTRL</name>
|
|
<description>Interrupt Control and State</description>
|
|
<addressOffset>0x00000D04</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_VEC_ACT</name>
|
|
<description>Interrupt Pending Vector Number</description>
|
|
<bitRange>[5:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_RET_BASE</name>
|
|
<description>Return to Base</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_VEC_PEN</name>
|
|
<description>Interrupt Pending Vector Number</description>
|
|
<bitRange>[17:12]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_NMI</name>
|
|
<description>NMI</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_HARD</name>
|
|
<description>Hard fault</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_MEM</name>
|
|
<description>Memory management fault</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_BUS</name>
|
|
<description>Bus fault</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_USG</name>
|
|
<description>Usage fault</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_SVC</name>
|
|
<description>SVCall</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_PNDSV</name>
|
|
<description>PendSV</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_INT_CTRL_VEC_PEN_TICK</name>
|
|
<description>SysTick</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_ISR_PEND</name>
|
|
<description>Interrupt Pending</description>
|
|
<bitRange>[22:22]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_ISR_PRE</name>
|
|
<description>Debug Interrupt Handling</description>
|
|
<bitRange>[23:23]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_PENDSTCLR</name>
|
|
<description>SysTick Clear Pending</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_PENDSTSET</name>
|
|
<description>SysTick Set Pending</description>
|
|
<bitRange>[26:26]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_UNPEND_SV</name>
|
|
<description>PendSV Clear Pending</description>
|
|
<bitRange>[27:27]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_PEND_SV</name>
|
|
<description>PendSV Set Pending</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_INT_CTRL_NMI_SET</name>
|
|
<description>NMI Set Pending</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTABLE</name>
|
|
<description>Vector Table Offset</description>
|
|
<addressOffset>0x00000D08</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_VTABLE_OFFSET</name>
|
|
<description>Vector Table Offset</description>
|
|
<bitRange>[28:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_VTABLE_BASE</name>
|
|
<description>Vector Table Base</description>
|
|
<bitRange>[29:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APINT</name>
|
|
<description>Application Interrupt and Reset Control</description>
|
|
<addressOffset>0x00000D0C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_APINT_VECT_RESET</name>
|
|
<description>System Reset</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_APINT_VECT_CLR_ACT</name>
|
|
<description>Clear Active NMI / Fault</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_APINT_SYSRESETREQ</name>
|
|
<description>System Reset Request</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_APINT_PRIGROUP</name>
|
|
<description>Interrupt Priority Grouping</description>
|
|
<bitRange>[10:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_7_1</name>
|
|
<description>Priority group 7.1 split</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_6_2</name>
|
|
<description>Priority group 6.2 split</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_5_3</name>
|
|
<description>Priority group 5.3 split</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_4_4</name>
|
|
<description>Priority group 4.4 split</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_3_5</name>
|
|
<description>Priority group 3.5 split</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_2_6</name>
|
|
<description>Priority group 2.6 split</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_1_7</name>
|
|
<description>Priority group 1.7 split</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_PRIGROUP_0_8</name>
|
|
<description>Priority group 0.8 split</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_APINT_ENDIANESS</name>
|
|
<description>Data Endianess</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_APINT_VECTKEY</name>
|
|
<description>Register Key</description>
|
|
<bitRange>[31:16]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_APINT_VECTKEY</name>
|
|
<description>Vector key</description>
|
|
<value>0x5fa</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_CTRL</name>
|
|
<description>System Control</description>
|
|
<addressOffset>0x00000D10</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SYS_CTRL_SLEEPEXIT</name>
|
|
<description>Sleep on ISR Exit</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_CTRL_SLEEPDEEP</name>
|
|
<description>Deep Sleep Enable</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_CTRL_SEVONPEND</name>
|
|
<description>Wake Up on Pending</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG_CTRL</name>
|
|
<description>Configuration and Control</description>
|
|
<addressOffset>0x00000D14</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_BASE_THR</name>
|
|
<description>Thread State Control</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_MAIN_PEND</name>
|
|
<description>Allow Main Interrupt Trigger</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_UNALIGNED</name>
|
|
<description>Trap on Unaligned Access</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_DIV0</name>
|
|
<description>Trap on Divide by 0</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_BFHFNMIGN</name>
|
|
<description>Ignore Bus Fault in NMI and Fault</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_CFG_CTRL_STKALIGN</name>
|
|
<description>Stack Alignment on Exception Entry</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_PRI1</name>
|
|
<description>System Handler Priority 1</description>
|
|
<addressOffset>0x00000D18</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SYS_PRI1_MEM</name>
|
|
<description>Memory Management Fault Priority</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_PRI1_BUS</name>
|
|
<description>Bus Fault Priority</description>
|
|
<bitRange>[15:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_PRI1_USAGE</name>
|
|
<description>Usage Fault Priority</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_PRI2</name>
|
|
<description>System Handler Priority 2</description>
|
|
<addressOffset>0x00000D1C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SYS_PRI2_SVC</name>
|
|
<description>SVCall Priority</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_PRI3</name>
|
|
<description>System Handler Priority 3</description>
|
|
<addressOffset>0x00000D20</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SYS_PRI3_DEBUG</name>
|
|
<description>Debug Priority</description>
|
|
<bitRange>[7:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_PRI3_PENDSV</name>
|
|
<description>PendSV Priority</description>
|
|
<bitRange>[23:21]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_PRI3_TICK</name>
|
|
<description>SysTick Exception Priority</description>
|
|
<bitRange>[31:29]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SYS_HND_CTRL</name>
|
|
<description>System Handler Control and State</description>
|
|
<addressOffset>0x00000D24</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_MEMA</name>
|
|
<description>Memory Management Fault Active</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_BUSA</name>
|
|
<description>Bus Fault Active</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_USGA</name>
|
|
<description>Usage Fault Active</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_SVCA</name>
|
|
<description>SVC Call Active</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_MON</name>
|
|
<description>Debug Monitor Active</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_PNDSV</name>
|
|
<description>PendSV Exception Active</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_TICK</name>
|
|
<description>SysTick Exception Active</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_USAGEP</name>
|
|
<description>Usage Fault Pending</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_MEMP</name>
|
|
<description>Memory Management Fault Pending</description>
|
|
<bitRange>[13:13]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_BUSP</name>
|
|
<description>Bus Fault Pending</description>
|
|
<bitRange>[14:14]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_SVC</name>
|
|
<description>SVC Call Pending</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_MEM</name>
|
|
<description>Memory Management Fault Enable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_BUS</name>
|
|
<description>Bus Fault Enable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_SYS_HND_CTRL_USAGE</name>
|
|
<description>Usage Fault Enable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULT_STAT</name>
|
|
<description>Configurable Fault Status</description>
|
|
<addressOffset>0x00000D28</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_IERR</name>
|
|
<description>Instruction Access Violation</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_DERR</name>
|
|
<description>Data Access Violation</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_MUSTKE</name>
|
|
<description>Unstack Access Violation</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_MSTKE</name>
|
|
<description>Stack Access Violation</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_MMARV</name>
|
|
<description>Memory Management Fault Address Register Valid</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_IBUS</name>
|
|
<description>Instruction Bus Error</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_PRECISE</name>
|
|
<description>Precise Data Bus Error</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_IMPRE</name>
|
|
<description>Imprecise Data Bus Error</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_BUSTKE</name>
|
|
<description>Unstack Bus Fault</description>
|
|
<bitRange>[11:11]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_BSTKE</name>
|
|
<description>Stack Bus Fault</description>
|
|
<bitRange>[12:12]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_BFARV</name>
|
|
<description>Bus Fault Address Register Valid</description>
|
|
<bitRange>[15:15]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_UNDEF</name>
|
|
<description>Undefined Instruction Usage Fault</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_INVSTAT</name>
|
|
<description>Invalid State Usage Fault</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_INVPC</name>
|
|
<description>Invalid PC Load Usage Fault</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_NOCP</name>
|
|
<description>No Coprocessor Usage Fault</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_UNALIGN</name>
|
|
<description>Unaligned Access Usage Fault</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_FAULT_STAT_DIV0</name>
|
|
<description>Divide-by-Zero Usage Fault</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFAULT_STAT</name>
|
|
<description>Hard Fault Status</description>
|
|
<addressOffset>0x00000D2C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_HFAULT_STAT_VECT</name>
|
|
<description>Vector Table Read Fault</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_HFAULT_STAT_FORCED</name>
|
|
<description>Forced Hard Fault</description>
|
|
<bitRange>[30:30]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_HFAULT_STAT_DBG</name>
|
|
<description>Debug Event</description>
|
|
<bitRange>[31:31]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEBUG_STAT</name>
|
|
<description>Debug Status Register</description>
|
|
<addressOffset>0x00000D30</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DEBUG_STAT_HALTED</name>
|
|
<description>Halt request</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DEBUG_STAT_BKPT</name>
|
|
<description>Breakpoint instruction</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DEBUG_STAT_DWTTRAP</name>
|
|
<description>DWT match</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DEBUG_STAT_VCATCH</name>
|
|
<description>Vector catch</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DEBUG_STAT_EXTRNL</name>
|
|
<description>EDBGRQ asserted</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MM_ADDR</name>
|
|
<description>Memory Management Fault Address</description>
|
|
<addressOffset>0x00000D34</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MM_ADDR</name>
|
|
<description>Fault Address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FAULT_ADDR</name>
|
|
<description>Bus Fault Address</description>
|
|
<addressOffset>0x00000D38</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_FAULT_ADDR</name>
|
|
<description>Fault Address</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_TYPE</name>
|
|
<description>MPU Type</description>
|
|
<addressOffset>0x00000D90</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_TYPE_SEPARATE</name>
|
|
<description>Separate or Unified MPU</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_TYPE_DREGION</name>
|
|
<description>Number of D Regions</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_TYPE_IREGION</name>
|
|
<description>Number of I Regions</description>
|
|
<bitRange>[23:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_CTRL</name>
|
|
<description>MPU Control</description>
|
|
<addressOffset>0x00000D94</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_CTRL_ENABLE</name>
|
|
<description>MPU Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_CTRL_HFNMIENA</name>
|
|
<description>MPU Enabled During Faults</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_CTRL_PRIVDEFEN</name>
|
|
<description>MPU Default Region</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_NUMBER</name>
|
|
<description>MPU Region Number</description>
|
|
<addressOffset>0x00000D98</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_NUMBER</name>
|
|
<description>MPU Region to Access</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_BASE</name>
|
|
<description>MPU Region Base Address</description>
|
|
<addressOffset>0x00000D9C</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_BASE_REGION</name>
|
|
<description>Region Number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE_VALID</name>
|
|
<description>Region Number Valid</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE_ADDR</name>
|
|
<description>Base Address Mask</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_ATTR</name>
|
|
<description>MPU Region Attribute and Size</description>
|
|
<addressOffset>0x00000DA0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_SIZE</name>
|
|
<description>Region Size Mask</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_32B</name>
|
|
<description>Region size 32 bytes</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_64B</name>
|
|
<description>Region size 64 bytes</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_128B</name>
|
|
<description>Region size 128 bytes</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_256B</name>
|
|
<description>Region size 256 bytes</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_512B</name>
|
|
<description>Region size 512 bytes</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_1K</name>
|
|
<description>Region size 1 Kbytes</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_2K</name>
|
|
<description>Region size 2 Kbytes</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_4K</name>
|
|
<description>Region size 4 Kbytes</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_8K</name>
|
|
<description>Region size 8 Kbytes</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_16K</name>
|
|
<description>Region size 16 Kbytes</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_32K</name>
|
|
<description>Region size 32 Kbytes</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_64K</name>
|
|
<description>Region size 64 Kbytes</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_128K</name>
|
|
<description>Region size 128 Kbytes</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_256K</name>
|
|
<description>Region size 256 Kbytes</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_512K</name>
|
|
<description>Region size 512 Kbytes</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_1M</name>
|
|
<description>Region size 1 Mbytes</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_2M</name>
|
|
<description>Region size 2 Mbytes</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_4M</name>
|
|
<description>Region size 4 Mbytes</description>
|
|
<value>0x15</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_8M</name>
|
|
<description>Region size 8 Mbytes</description>
|
|
<value>0x16</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_16M</name>
|
|
<description>Region size 16 Mbytes</description>
|
|
<value>0x17</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_32M</name>
|
|
<description>Region size 32 Mbytes</description>
|
|
<value>0x18</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_64M</name>
|
|
<description>Region size 64 Mbytes</description>
|
|
<value>0x19</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_128M</name>
|
|
<description>Region size 128 Mbytes</description>
|
|
<value>0x1a</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_256M</name>
|
|
<description>Region size 256 Mbytes</description>
|
|
<value>0x1b</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_512M</name>
|
|
<description>Region size 512 Mbytes</description>
|
|
<value>0x1c</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_1G</name>
|
|
<description>Region size 1 Gbytes</description>
|
|
<value>0x1d</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_2G</name>
|
|
<description>Region size 2 Gbytes</description>
|
|
<value>0x1e</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SIZE_4G</name>
|
|
<description>Region size 4 Gbytes</description>
|
|
<value>0x1f</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_SRD</name>
|
|
<description>Subregion Disable Bits</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_0</name>
|
|
<description>Sub-region 0 disable</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_1</name>
|
|
<description>Sub-region 1 disable</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_2</name>
|
|
<description>Sub-region 2 disable</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_3</name>
|
|
<description>Sub-region 3 disable</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_4</name>
|
|
<description>Sub-region 4 disable</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_5</name>
|
|
<description>Sub-region 5 disable</description>
|
|
<value>0x20</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_6</name>
|
|
<description>Sub-region 6 disable</description>
|
|
<value>0x40</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_SRD_7</name>
|
|
<description>Sub-region 7 disable</description>
|
|
<value>0x80</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_BUFFRABLE</name>
|
|
<description>Bufferable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_CACHEABLE</name>
|
|
<description>Cacheable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_SHAREABLE</name>
|
|
<description>Shareable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_TEX</name>
|
|
<description>Type Extension Mask</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_AP</name>
|
|
<description>Access Privilege</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_NO_NO</name>
|
|
<description>prv: no access, usr: no access</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_RW_NO</name>
|
|
<description>prv: rw, usr: none</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_RW_RO</name>
|
|
<description>prv: rw, usr: read-only</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_RW_RW</name>
|
|
<description>prv: rw, usr: rw</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_RO_NO</name>
|
|
<description>prv: ro, usr: none</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_MPU_ATTR_AP_RO_RO</name>
|
|
<description>prv: ro, usr: ro</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR_XN</name>
|
|
<description>Instruction Access Disable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_BASE1</name>
|
|
<description>MPU Region Base Address Alias 1</description>
|
|
<addressOffset>0x00000DA4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_BASE1_REGION</name>
|
|
<description>Region Number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE1_VALID</name>
|
|
<description>Region Number Valid</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE1_ADDR</name>
|
|
<description>Base Address Mask</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_ATTR1</name>
|
|
<description>MPU Region Attribute and Size Alias 1</description>
|
|
<addressOffset>0x00000DA8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_SIZE</name>
|
|
<description>Region Size Mask</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_SRD</name>
|
|
<description>Subregion Disable Bits</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_BUFFRABLE</name>
|
|
<description>Bufferable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_CACHEABLE</name>
|
|
<description>Cacheable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_SHAREABLE</name>
|
|
<description>Shareable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_TEX</name>
|
|
<description>Type Extension Mask</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_AP</name>
|
|
<description>Access Privilege</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR1_XN</name>
|
|
<description>Instruction Access Disable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_BASE2</name>
|
|
<description>MPU Region Base Address Alias 2</description>
|
|
<addressOffset>0x00000DAC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_BASE2_REGION</name>
|
|
<description>Region Number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE2_VALID</name>
|
|
<description>Region Number Valid</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE2_ADDR</name>
|
|
<description>Base Address Mask</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_ATTR2</name>
|
|
<description>MPU Region Attribute and Size Alias 2</description>
|
|
<addressOffset>0x00000DB0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_SIZE</name>
|
|
<description>Region Size Mask</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_SRD</name>
|
|
<description>Subregion Disable Bits</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_BUFFRABLE</name>
|
|
<description>Bufferable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_CACHEABLE</name>
|
|
<description>Cacheable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_SHAREABLE</name>
|
|
<description>Shareable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_TEX</name>
|
|
<description>Type Extension Mask</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_AP</name>
|
|
<description>Access Privilege</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR2_XN</name>
|
|
<description>Instruction Access Disable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_BASE3</name>
|
|
<description>MPU Region Base Address Alias 3</description>
|
|
<addressOffset>0x00000DB4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_BASE3_REGION</name>
|
|
<description>Region Number</description>
|
|
<bitRange>[2:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE3_VALID</name>
|
|
<description>Region Number Valid</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_BASE3_ADDR</name>
|
|
<description>Base Address Mask</description>
|
|
<bitRange>[31:5]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPU_ATTR3</name>
|
|
<description>MPU Region Attribute and Size Alias 3</description>
|
|
<addressOffset>0x00000DB8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_ENABLE</name>
|
|
<description>Region Enable</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_SIZE</name>
|
|
<description>Region Size Mask</description>
|
|
<bitRange>[5:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_SRD</name>
|
|
<description>Subregion Disable Bits</description>
|
|
<bitRange>[15:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_BUFFRABLE</name>
|
|
<description>Bufferable</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_CACHEABLE</name>
|
|
<description>Cacheable</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_SHAREABLE</name>
|
|
<description>Shareable</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_TEX</name>
|
|
<description>Type Extension Mask</description>
|
|
<bitRange>[21:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_AP</name>
|
|
<description>Access Privilege</description>
|
|
<bitRange>[26:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_MPU_ATTR3_XN</name>
|
|
<description>Instruction Access Disable</description>
|
|
<bitRange>[28:28]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBG_CTRL</name>
|
|
<description>Debug Control and Status Reg</description>
|
|
<addressOffset>0x00000DF0</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_C_DEBUGEN</name>
|
|
<description>Enable debug</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_C_HALT</name>
|
|
<description>Halt the core</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_C_STEP</name>
|
|
<description>Step the core</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_C_MASKINT</name>
|
|
<description>Mask interrupts when stepping</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_C_SNAPSTALL</name>
|
|
<description>Breaks a stalled load/store</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_REGRDY</name>
|
|
<description>Register read/write available</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_HALT</name>
|
|
<description>Core status on halt</description>
|
|
<bitRange>[17:17]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_SLEEP</name>
|
|
<description>Core is sleeping</description>
|
|
<bitRange>[18:18]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_LOCKUP</name>
|
|
<description>Core is locked up</description>
|
|
<bitRange>[19:19]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_RETIRE_ST</name>
|
|
<description>Core has executed insruction since last read</description>
|
|
<bitRange>[24:24]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_CTRL_S_RESET_ST</name>
|
|
<description>Core has reset since last read</description>
|
|
<bitRange>[25:25]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBG_XFER</name>
|
|
<description>Debug Core Reg. Transfer Select</description>
|
|
<addressOffset>0x00000DF4</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DBG_XFER_REG_SEL</name>
|
|
<description>Register</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<enumeratedValues>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R0</name>
|
|
<description>Register R0</description>
|
|
<value>0x0</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R1</name>
|
|
<description>Register R1</description>
|
|
<value>0x1</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R2</name>
|
|
<description>Register R2</description>
|
|
<value>0x2</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R3</name>
|
|
<description>Register R3</description>
|
|
<value>0x3</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R4</name>
|
|
<description>Register R4</description>
|
|
<value>0x4</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R5</name>
|
|
<description>Register R5</description>
|
|
<value>0x5</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R6</name>
|
|
<description>Register R6</description>
|
|
<value>0x6</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R7</name>
|
|
<description>Register R7</description>
|
|
<value>0x7</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R8</name>
|
|
<description>Register R8</description>
|
|
<value>0x8</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R9</name>
|
|
<description>Register R9</description>
|
|
<value>0x9</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R10</name>
|
|
<description>Register R10</description>
|
|
<value>0xa</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R11</name>
|
|
<description>Register R11</description>
|
|
<value>0xb</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R12</name>
|
|
<description>Register R12</description>
|
|
<value>0xc</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R13</name>
|
|
<description>Register R13</description>
|
|
<value>0xd</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R14</name>
|
|
<description>Register R14</description>
|
|
<value>0xe</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_R15</name>
|
|
<description>Register R15</description>
|
|
<value>0xf</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_FLAGS</name>
|
|
<description>xPSR/Flags register</description>
|
|
<value>0x10</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_MSP</name>
|
|
<description>Main SP</description>
|
|
<value>0x11</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_PSP</name>
|
|
<description>Process SP</description>
|
|
<value>0x12</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_DSP</name>
|
|
<description>Deep SP</description>
|
|
<value>0x13</value>
|
|
</enumeratedValue>
|
|
<enumeratedValue>
|
|
<name>NVIC_DBG_XFER_REG_CFBP</name>
|
|
<description>Control/Fault/BasePri/PriMask</description>
|
|
<value>0x14</value>
|
|
</enumeratedValue>
|
|
</enumeratedValues>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_XFER_REG_WNR</name>
|
|
<description>Write or not read</description>
|
|
<bitRange>[16:16]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBG_DATA</name>
|
|
<description>Debug Core Register Data</description>
|
|
<addressOffset>0x00000DF8</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DBG_DATA</name>
|
|
<description>Data temporary cache</description>
|
|
<bitRange>[31:0]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBG_INT</name>
|
|
<description>Debug Reset Interrupt Control</description>
|
|
<addressOffset>0x00000DFC</addressOffset>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_DBG_INT_RSTVCATCH</name>
|
|
<description>Reset vector catch</description>
|
|
<bitRange>[0:0]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_RSTPENDING</name>
|
|
<description>Core reset is pending</description>
|
|
<bitRange>[1:1]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_RSTPENDCLR</name>
|
|
<description>Clear pending core reset</description>
|
|
<bitRange>[2:2]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_RESET</name>
|
|
<description>Core reset status</description>
|
|
<bitRange>[3:3]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_MMERR</name>
|
|
<description>Debug trap on mem manage fault</description>
|
|
<bitRange>[4:4]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_NOCPERR</name>
|
|
<description>Debug trap on coprocessor error</description>
|
|
<bitRange>[5:5]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_CHKERR</name>
|
|
<description>Debug trap on usage fault check</description>
|
|
<bitRange>[6:6]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_STATERR</name>
|
|
<description>Debug trap on usage fault state</description>
|
|
<bitRange>[7:7]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_BUSERR</name>
|
|
<description>Debug trap on bus error</description>
|
|
<bitRange>[8:8]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_INTERR</name>
|
|
<description>Debug trap on interrupt errors</description>
|
|
<bitRange>[9:9]</bitRange>
|
|
</field>
|
|
<field>
|
|
<name>NVIC_DBG_INT_HARDERR</name>
|
|
<description>Debug trap on hard fault</description>
|
|
<bitRange>[10:10]</bitRange>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SW_TRIG</name>
|
|
<description>Software Trigger Interrupt</description>
|
|
<addressOffset>0x00000F00</addressOffset>
|
|
<access>write-only</access>
|
|
<fields>
|
|
<field>
|
|
<name>NVIC_SW_TRIG_INTID</name>
|
|
<description>Interrupt ID</description>
|
|
<bitRange>[4:0]</bitRange>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
<vendorExtensions>
|
|
<memory>
|
|
<name>FLASH</name>
|
|
<description>FLASH Memory Map for lm3s811</description>
|
|
<baseAddress>0x00000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00010000</size>
|
|
<usage>FLASH Memory</usage>
|
|
</addressBlock>
|
|
</memory>
|
|
<memory>
|
|
<name>SRAM</name>
|
|
<description>SRAM Memory Map for lm3s811</description>
|
|
<baseAddress>0x20000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0</offset>
|
|
<size>0x00002000</size>
|
|
<usage>SRAM</usage>
|
|
</addressBlock>
|
|
</memory>
|
|
</vendorExtensions>
|
|
</device>
|