LM3S6965 7944 ARM Cortex-M3 Stellaris Device 8 32 32 read-write 0 0 WATCHDOG0 Register map for WATCHDOG0 peripheral WATCHDOG WATCHDOG0 0x40000000 0 0x00001000 registers LOAD Watchdog Load 0x00000000 WDT_LOAD Watchdog Load Value [31:0] VALUE Watchdog Value 0x00000004 WDT_VALUE Watchdog Value [31:0] CTL Watchdog Control 0x00000008 WDT_CTL_INTEN Watchdog Interrupt Enable [0:0] WDT_CTL_RESEN Watchdog Reset Enable [1:1] ICR Watchdog Interrupt Clear 0x0000000C write-only WDT_ICR Watchdog Interrupt Clear [31:0] write-only RIS Watchdog Raw Interrupt Status 0x00000010 WDT_RIS_WDTRIS Watchdog Raw Interrupt Status [0:0] MIS Watchdog Masked Interrupt Status 0x00000014 WDT_MIS_WDTMIS Watchdog Masked Interrupt Status [0:0] TEST Watchdog Test 0x00000418 WDT_TEST_STALL Watchdog Stall Enable [8:8] LOCK Watchdog Lock 0x00000C00 WDT_LOCK Watchdog Lock [31:0] WDT_LOCK_UNLOCKED Unlocked 0x0 WDT_LOCK_LOCKED Locked 0x1 WDT_LOCK_UNLOCK Unlocks the watchdog timer 0x1acce551 GPIO_PORTA Register map for GPIO_PORTA peripheral GPIO_PORT GPIO_PORTA 0x40004000 0 0x00001000 registers DATA GPIO Data 0x000003FC DIR GPIO Direction 0x00000400 IS GPIO Interrupt Sense 0x00000404 IBE GPIO Interrupt Both Edges 0x00000408 IEV GPIO Interrupt Event 0x0000040C IM GPIO Interrupt Mask 0x00000410 RIS GPIO Raw Interrupt Status 0x00000414 MIS GPIO Masked Interrupt Status 0x00000418 ICR GPIO Interrupt Clear 0x0000041C write-only AFSEL GPIO Alternate Function Select 0x00000420 DR2R GPIO 2-mA Drive Select 0x00000500 DR4R GPIO 4-mA Drive Select 0x00000504 DR8R GPIO 8-mA Drive Select 0x00000508 ODR GPIO Open Drain Select 0x0000050C PUR GPIO Pull-Up Select 0x00000510 PDR GPIO Pull-Down Select 0x00000514 SLR GPIO Slew Rate Control Select 0x00000518 DEN GPIO Digital Enable 0x0000051C LOCK GPIO Lock 0x00000520 GPIO_LOCK GPIO Lock [31:0] GPIO_LOCK_UNLOCKED The GPIOCR register is unlocked and may be modified 0x0 GPIO_LOCK_LOCKED The GPIOCR register is locked and may not be modified 0x1 GPIO_LOCK_KEY Unlocks the GPIO_CR register 0x1acce551 CR GPIO Commit 0x00000524 read-only GPIO_PORTB GPIO_PORTB 0x40005000 GPIO_PORTC GPIO_PORTC 0x40006000 GPIO_PORTD GPIO_PORTD 0x40007000 SSI0 Register map for SSI0 peripheral SSI SSI0 0x40008000 0 0x00001000 registers CR0 SSI Control 0 0x00000000 SSI_CR0_DSS SSI Data Size Select [3:0] SSI_CR0_DSS_4 4-bit data 0x3 SSI_CR0_DSS_5 5-bit data 0x4 SSI_CR0_DSS_6 6-bit data 0x5 SSI_CR0_DSS_7 7-bit data 0x6 SSI_CR0_DSS_8 8-bit data 0x7 SSI_CR0_DSS_9 9-bit data 0x8 SSI_CR0_DSS_10 10-bit data 0x9 SSI_CR0_DSS_11 11-bit data 0xa SSI_CR0_DSS_12 12-bit data 0xb SSI_CR0_DSS_13 13-bit data 0xc SSI_CR0_DSS_14 14-bit data 0xd SSI_CR0_DSS_15 15-bit data 0xe SSI_CR0_DSS_16 16-bit data 0xf SSI_CR0_FRF SSI Frame Format Select [5:4] SSI_CR0_FRF_MOTO Freescale SPI Frame Format 0x0 SSI_CR0_FRF_TI Texas Instruments Synchronous Serial Frame Format 0x1 SSI_CR0_FRF_NMW MICROWIRE Frame Format 0x2 SSI_CR0_SPO SSI Serial Clock Polarity [6:6] SSI_CR0_SPH SSI Serial Clock Phase [7:7] SSI_CR0_SCR SSI Serial Clock Rate [15:8] CR1 SSI Control 1 0x00000004 SSI_CR1_LBM SSI Loopback Mode [0:0] SSI_CR1_SSE SSI Synchronous Serial Port Enable [1:1] SSI_CR1_MS SSI Master/Slave Select [2:2] SSI_CR1_SOD SSI Slave Mode Output Disable [3:3] DR SSI Data 0x00000008 SSI_DR_DATA SSI Receive/Transmit Data [15:0] SR SSI Status 0x0000000C SSI_SR_TFE SSI Transmit FIFO Empty [0:0] SSI_SR_TNF SSI Transmit FIFO Not Full [1:1] SSI_SR_RNE SSI Receive FIFO Not Empty [2:2] SSI_SR_RFF SSI Receive FIFO Full [3:3] SSI_SR_BSY SSI Busy Bit [4:4] CPSR SSI Clock Prescale 0x00000010 SSI_CPSR_CPSDVSR SSI Clock Prescale Divisor [7:0] IM SSI Interrupt Mask 0x00000014 SSI_IM_RORIM SSI Receive Overrun Interrupt Mask [0:0] SSI_IM_RTIM SSI Receive Time-Out Interrupt Mask [1:1] SSI_IM_RXIM SSI Receive FIFO Interrupt Mask [2:2] SSI_IM_TXIM SSI Transmit FIFO Interrupt Mask [3:3] RIS SSI Raw Interrupt Status 0x00000018 SSI_RIS_RORRIS SSI Receive Overrun Raw Interrupt Status [0:0] SSI_RIS_RTRIS SSI Receive Time-Out Raw Interrupt Status [1:1] SSI_RIS_RXRIS SSI Receive FIFO Raw Interrupt Status [2:2] SSI_RIS_TXRIS SSI Transmit FIFO Raw Interrupt Status [3:3] MIS SSI Masked Interrupt Status 0x0000001C SSI_MIS_RORMIS SSI Receive Overrun Masked Interrupt Status [0:0] SSI_MIS_RTMIS SSI Receive Time-Out Masked Interrupt Status [1:1] SSI_MIS_RXMIS SSI Receive FIFO Masked Interrupt Status [2:2] SSI_MIS_TXMIS SSI Transmit FIFO Masked Interrupt Status [3:3] ICR SSI Interrupt Clear 0x00000020 write-only SSI_ICR_RORIC SSI Receive Overrun Interrupt Clear [0:0] write-only SSI_ICR_RTIC SSI Receive Time-Out Interrupt Clear [1:1] write-only UART0 Register map for UART0 peripheral UART UART0 0x4000C000 0 0x00001000 registers DR UART Data 0x00000000 UART_DR_DATA Data Transmitted or Received [7:0] UART_DR_FE UART Framing Error [8:8] UART_DR_PE UART Parity Error [9:9] UART_DR_BE UART Break Error [10:10] UART_DR_OE UART Overrun Error [11:11] RSR UART Receive Status/Error Clear 0x00000004 UART_RSR_FE UART Framing Error [0:0] UART_RSR_PE UART Parity Error [1:1] UART_RSR_BE UART Break Error [2:2] UART_RSR_OE UART Overrun Error [3:3] ECR UART Receive Status/Error Clear UART_ALT 0x00000004 UART_ECR_DATA Error Clear [7:0] FR UART Flag 0x00000018 UART_FR_BUSY UART Busy [3:3] UART_FR_RXFE UART Receive FIFO Empty [4:4] UART_FR_TXFF UART Transmit FIFO Full [5:5] UART_FR_RXFF UART Receive FIFO Full [6:6] UART_FR_TXFE UART Transmit FIFO Empty [7:7] ILPR UART IrDA Low-Power Register 0x00000020 UART_ILPR_ILPDVSR IrDA Low-Power Divisor [7:0] IBRD UART Integer Baud-Rate Divisor 0x00000024 UART_IBRD_DIVINT Integer Baud-Rate Divisor [15:0] FBRD UART Fractional Baud-Rate Divisor 0x00000028 UART_FBRD_DIVFRAC Fractional Baud-Rate Divisor [5:0] LCRH UART Line Control 0x0000002C UART_LCRH_BRK UART Send Break [0:0] UART_LCRH_PEN UART Parity Enable [1:1] UART_LCRH_EPS UART Even Parity Select [2:2] UART_LCRH_STP2 UART Two Stop Bits Select [3:3] UART_LCRH_FEN UART Enable FIFOs [4:4] UART_LCRH_WLEN UART Word Length [6:5] UART_LCRH_WLEN_5 5 bits (default) 0x0 UART_LCRH_WLEN_6 6 bits 0x1 UART_LCRH_WLEN_7 7 bits 0x2 UART_LCRH_WLEN_8 8 bits 0x3 UART_LCRH_SPS UART Stick Parity Select [7:7] CTL UART Control 0x00000030 UART_CTL_UARTEN UART Enable [0:0] UART_CTL_SIREN UART SIR Enable [1:1] UART_CTL_SIRLP UART SIR Low-Power Mode [2:2] UART_CTL_LBE UART Loop Back Enable [7:7] UART_CTL_TXE UART Transmit Enable [8:8] UART_CTL_RXE UART Receive Enable [9:9] IFLS UART Interrupt FIFO Level Select 0x00000034 UART_IFLS_TX UART Transmit Interrupt FIFO Level Select [2:0] UART_IFLS_TX1_8 TX FIFO <= 1/8 full 0x0 UART_IFLS_TX2_8 TX FIFO <= 1/4 full 0x1 UART_IFLS_TX4_8 TX FIFO <= 1/2 full (default) 0x2 UART_IFLS_TX6_8 TX FIFO <= 3/4 full 0x3 UART_IFLS_TX7_8 TX FIFO <= 7/8 full 0x4 UART_IFLS_RX UART Receive Interrupt FIFO Level Select [5:3] UART_IFLS_RX1_8 RX FIFO >= 1/8 full 0x0 UART_IFLS_RX2_8 RX FIFO >= 1/4 full 0x1 UART_IFLS_RX4_8 RX FIFO >= 1/2 full (default) 0x2 UART_IFLS_RX6_8 RX FIFO >= 3/4 full 0x3 UART_IFLS_RX7_8 RX FIFO >= 7/8 full 0x4 IM UART Interrupt Mask 0x00000038 UART_IM_RXIM UART Receive Interrupt Mask [4:4] UART_IM_TXIM UART Transmit Interrupt Mask [5:5] UART_IM_RTIM UART Receive Time-Out Interrupt Mask [6:6] UART_IM_FEIM UART Framing Error Interrupt Mask [7:7] UART_IM_PEIM UART Parity Error Interrupt Mask [8:8] UART_IM_BEIM UART Break Error Interrupt Mask [9:9] UART_IM_OEIM UART Overrun Error Interrupt Mask [10:10] RIS UART Raw Interrupt Status 0x0000003C UART_RIS_RXRIS UART Receive Raw Interrupt Status [4:4] UART_RIS_TXRIS UART Transmit Raw Interrupt Status [5:5] UART_RIS_RTRIS UART Receive Time-Out Raw Interrupt Status [6:6] UART_RIS_FERIS UART Framing Error Raw Interrupt Status [7:7] UART_RIS_PERIS UART Parity Error Raw Interrupt Status [8:8] UART_RIS_BERIS UART Break Error Raw Interrupt Status [9:9] UART_RIS_OERIS UART Overrun Error Raw Interrupt Status [10:10] MIS UART Masked Interrupt Status 0x00000040 UART_MIS_RXMIS UART Receive Masked Interrupt Status [4:4] UART_MIS_TXMIS UART Transmit Masked Interrupt Status [5:5] UART_MIS_RTMIS UART Receive Time-Out Masked Interrupt Status [6:6] UART_MIS_FEMIS UART Framing Error Masked Interrupt Status [7:7] UART_MIS_PEMIS UART Parity Error Masked Interrupt Status [8:8] UART_MIS_BEMIS UART Break Error Masked Interrupt Status [9:9] UART_MIS_OEMIS UART Overrun Error Masked Interrupt Status [10:10] ICR UART Interrupt Clear 0x00000044 write-only UART_ICR_RXIC Receive Interrupt Clear [4:4] write-only UART_ICR_TXIC Transmit Interrupt Clear [5:5] write-only UART_ICR_RTIC Receive Time-Out Interrupt Clear [6:6] write-only UART_ICR_FEIC Framing Error Interrupt Clear [7:7] write-only UART_ICR_PEIC Parity Error Interrupt Clear [8:8] write-only UART_ICR_BEIC Break Error Interrupt Clear [9:9] write-only UART_ICR_OEIC Overrun Error Interrupt Clear [10:10] write-only UART1 UART1 0x4000D000 UART2 UART2 0x4000E000 I2C0 Register map for I2C0 peripheral I2C I2C0 0x40020000 0 0x00001000 registers MSA I2C Master Slave Address 0x00000000 I2C_MSA_RS Receive not send [0:0] I2C_MSA_SA I2C Slave Address [7:1] SOAR I2C Slave Own Address 0x00000800 I2C_SOAR_OAR I2C Slave Own Address [6:0] SCSR I2C Slave Control/Status 0x00000804 I2C_SCSR_RREQ Receive Request [0:0] I2C_SCSR_TREQ Transmit Request [1:1] I2C_SCSR_FBR First Byte Received [2:2] SCSR I2C Slave Control/Status I2C0_ALT 0x00000804 I2C_SCSR_DA Device Active [0:0] MCS I2C Master Control/Status 0x00000004 I2C_MCS_RUN I2C Master Enable [0:0] I2C_MCS_START Generate START [1:1] I2C_MCS_ADRACK Acknowledge Address [2:2] I2C_MCS_ACK Data Acknowledge Enable [3:3] I2C_MCS_ARBLST Arbitration Lost [4:4] I2C_MCS_IDLE I2C Idle [5:5] I2C_MCS_BUSBSY Bus Busy [6:6] MCS I2C Master Control/Status I2C0_ALT 0x00000004 I2C_MCS_BUSY I2C Busy [0:0] I2C_MCS_ERROR Error [1:1] I2C_MCS_STOP Generate STOP [2:2] I2C_MCS_DATACK Acknowledge Data [3:3] SDR I2C Slave Data 0x00000808 I2C_SDR_DATA Data for Transfer [7:0] MDR I2C Master Data 0x00000008 I2C_MDR_DATA Data Transferred [7:0] MTPR I2C Master Timer Period 0x0000000C I2C_MTPR_TPR SCL Clock Period [6:0] SIMR I2C Slave Interrupt Mask 0x0000080C I2C_SIMR_DATAIM Data Interrupt Mask [0:0] SRIS I2C Slave Raw Interrupt Status 0x00000810 I2C_SRIS_DATARIS Data Raw Interrupt Status [0:0] MIMR I2C Master Interrupt Mask 0x00000010 I2C_MIMR_IM Interrupt Mask [0:0] MRIS I2C Master Raw Interrupt Status 0x00000014 I2C_MRIS_RIS Raw Interrupt Status [0:0] SMIS I2C Slave Masked Interrupt Status 0x00000814 I2C_SMIS_DATAMIS Data Masked Interrupt Status [0:0] SICR I2C Slave Interrupt Clear 0x00000818 write-only I2C_SICR_DATAIC Data Interrupt Clear [0:0] write-only MMIS I2C Master Masked Interrupt Status 0x00000018 I2C_MMIS_MIS Masked Interrupt Status [0:0] MICR I2C Master Interrupt Clear 0x0000001C write-only I2C_MICR_IC Interrupt Clear [0:0] write-only MCR I2C Master Configuration 0x00000020 I2C_MCR_LPBK I2C Loopback [0:0] I2C_MCR_MFE I2C Master Function Enable [4:4] I2C_MCR_SFE I2C Slave Function Enable [5:5] I2C1 I2C1 0x40021000 GPIO_PORTE GPIO_PORTE 0x40024000 GPIO_PORTF GPIO_PORTF 0x40025000 GPIO_PORTG GPIO_PORTG 0x40026000 PWM0 Register map for PWM0 peripheral PWM PWM0 0x40028000 0 0x00001000 registers CTL PWM Master Control 0x00000000 PWM_CTL_GLOBALSYNC0 Update PWM Generator 0 [0:0] PWM_CTL_GLOBALSYNC1 Update PWM Generator 1 [1:1] PWM_CTL_GLOBALSYNC2 Update PWM Generator 2 [2:2] SYNC PWM Time Base Sync 0x00000004 PWM_SYNC_SYNC0 Reset Generator 0 Counter [0:0] PWM_SYNC_SYNC1 Reset Generator 1 Counter [1:1] PWM_SYNC_SYNC2 Reset Generator 2 Counter [2:2] ENABLE PWM Output Enable 0x00000008 PWM_ENABLE_PWM0EN PWM0 Output Enable [0:0] PWM_ENABLE_PWM1EN PWM1 Output Enable [1:1] PWM_ENABLE_PWM2EN PWM2 Output Enable [2:2] PWM_ENABLE_PWM3EN PWM3 Output Enable [3:3] PWM_ENABLE_PWM4EN PWM4 Output Enable [4:4] PWM_ENABLE_PWM5EN PWM5 Output Enable [5:5] INVERT PWM Output Inversion 0x0000000C PWM_INVERT_PWM0INV Invert PWM0 Signal [0:0] PWM_INVERT_PWM1INV Invert PWM1 Signal [1:1] PWM_INVERT_PWM2INV Invert PWM2 Signal [2:2] PWM_INVERT_PWM3INV Invert PWM3 Signal [3:3] PWM_INVERT_PWM4INV Invert PWM4 Signal [4:4] PWM_INVERT_PWM5INV Invert PWM5 Signal [5:5] FAULT PWM Output Fault 0x00000010 PWM_FAULT_FAULT0 PWM0 Fault [0:0] PWM_FAULT_FAULT1 PWM1 Fault [1:1] PWM_FAULT_FAULT2 PWM2 Fault [2:2] PWM_FAULT_FAULT3 PWM3 Fault [3:3] PWM_FAULT_FAULT4 PWM4 Fault [4:4] PWM_FAULT_FAULT5 PWM5 Fault [5:5] INTEN PWM Interrupt Enable 0x00000014 PWM_INTEN_INTPWM0 PWM0 Interrupt Enable [0:0] PWM_INTEN_INTPWM1 PWM1 Interrupt Enable [1:1] PWM_INTEN_INTPWM2 PWM2 Interrupt Enable [2:2] PWM_INTEN_INTFAULT Fault Interrupt Enable [16:16] RIS PWM Raw Interrupt Status 0x00000018 PWM_RIS_INTPWM0 PWM0 Interrupt Asserted [0:0] PWM_RIS_INTPWM1 PWM1 Interrupt Asserted [1:1] PWM_RIS_INTPWM2 PWM2 Interrupt Asserted [2:2] PWM_RIS_INTFAULT Fault Interrupt Asserted [16:16] ISC PWM Interrupt Status and Clear 0x0000001C PWM_ISC_INTPWM0 PWM0 Interrupt Status [0:0] PWM_ISC_INTPWM1 PWM1 Interrupt Status [1:1] PWM_ISC_INTPWM2 PWM2 Interrupt Status [2:2] PWM_ISC_INTFAULT Fault Interrupt Asserted [16:16] STATUS PWM Status 0x00000020 _0_CTL PWM0 Control 0x00000040 PWM_X_CTL_ENABLE PWM Block Enable [0:0] PWM_X_CTL_MODE Counter Mode [1:1] PWM_X_CTL_DEBUG Debug Mode [2:2] PWM_X_CTL_LOADUPD Load Register Update Mode [3:3] PWM_X_CTL_CMPAUPD Comparator A Update Mode [4:4] PWM_X_CTL_CMPBUPD Comparator B Update Mode [5:5] _0_INTEN PWM0 Interrupt and Trigger Enable 0x00000044 PWM_X_INTEN_INTCNTZERO Interrupt for Counter=0 [0:0] PWM_X_INTEN_INTCNTLOAD Interrupt for Counter=PWMnLOAD [1:1] PWM_X_INTEN_INTCMPAU Interrupt for Counter=PWMnCMPA Up [2:2] PWM_X_INTEN_INTCMPAD Interrupt for Counter=PWMnCMPA Down [3:3] PWM_X_INTEN_INTCMPBU Interrupt for Counter=PWMnCMPB Up [4:4] PWM_X_INTEN_INTCMPBD Interrupt for Counter=PWMnCMPB Down [5:5] PWM_X_INTEN_TRCNTZERO Trigger for Counter=0 [8:8] PWM_X_INTEN_TRCNTLOAD Trigger for Counter=PWMnLOAD [9:9] PWM_X_INTEN_TRCMPAU Trigger for Counter=PWMnCMPA Up [10:10] PWM_X_INTEN_TRCMPAD Trigger for Counter=PWMnCMPA Down [11:11] PWM_X_INTEN_TRCMPBU Trigger for Counter=PWMnCMPB Up [12:12] PWM_X_INTEN_TRCMPBD Trigger for Counter=PWMnCMPB Down [13:13] _0_RIS PWM0 Raw Interrupt Status 0x00000048 PWM_X_RIS_INTCNTZERO Counter=0 Interrupt Status [0:0] PWM_X_RIS_INTCNTLOAD Counter=Load Interrupt Status [1:1] PWM_X_RIS_INTCMPAU Comparator A Up Interrupt Status [2:2] PWM_X_RIS_INTCMPAD Comparator A Down Interrupt Status [3:3] PWM_X_RIS_INTCMPBU Comparator B Up Interrupt Status [4:4] PWM_X_RIS_INTCMPBD Comparator B Down Interrupt Status [5:5] _0_ISC PWM0 Interrupt Status and Clear 0x0000004C PWM_X_ISC_INTCNTZERO Counter=0 Interrupt [0:0] PWM_X_ISC_INTCNTLOAD Counter=Load Interrupt [1:1] PWM_X_ISC_INTCMPAU Comparator A Up Interrupt [2:2] PWM_X_ISC_INTCMPAD Comparator A Down Interrupt [3:3] PWM_X_ISC_INTCMPBU Comparator B Up Interrupt [4:4] PWM_X_ISC_INTCMPBD Comparator B Down Interrupt [5:5] _0_LOAD PWM0 Load 0x00000050 PWM_X_LOAD Counter Load Value [15:0] _0_COUNT PWM0 Counter 0x00000054 PWM_X_COUNT Counter Value [15:0] _0_CMPA PWM0 Compare A 0x00000058 PWM_X_CMPA Comparator A Value [15:0] _0_CMPB PWM0 Compare B 0x0000005C PWM_X_CMPB Comparator B Value [15:0] _0_GENA PWM0 Generator A Control 0x00000060 PWM_X_GENA_ACTZERO Action for Counter=0 [1:0] PWM_X_GENA_ACTZERO_NONE Do nothing 0x0 PWM_X_GENA_ACTZERO_INV Invert pwmA 0x1 PWM_X_GENA_ACTZERO_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTZERO_ONE Drive pwmA High 0x3 PWM_X_GENA_ACTLOAD Action for Counter=LOAD [3:2] PWM_X_GENA_ACTLOAD_NONE Do nothing 0x0 PWM_X_GENA_ACTLOAD_INV Invert pwmA 0x1 PWM_X_GENA_ACTLOAD_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTLOAD_ONE Drive pwmA High 0x3 PWM_X_GENA_ACTCMPAU Action for Comparator A Up [5:4] PWM_X_GENA_ACTCMPAU_NONE Do nothing 0x0 PWM_X_GENA_ACTCMPAU_INV Invert pwmA 0x1 PWM_X_GENA_ACTCMPAU_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTCMPAU_ONE Drive pwmA High 0x3 PWM_X_GENA_ACTCMPAD Action for Comparator A Down [7:6] PWM_X_GENA_ACTCMPAD_NONE Do nothing 0x0 PWM_X_GENA_ACTCMPAD_INV Invert pwmA 0x1 PWM_X_GENA_ACTCMPAD_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTCMPAD_ONE Drive pwmA High 0x3 PWM_X_GENA_ACTCMPBU Action for Comparator B Up [9:8] PWM_X_GENA_ACTCMPBU_NONE Do nothing 0x0 PWM_X_GENA_ACTCMPBU_INV Invert pwmA 0x1 PWM_X_GENA_ACTCMPBU_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTCMPBU_ONE Drive pwmA High 0x3 PWM_X_GENA_ACTCMPBD Action for Comparator B Down [11:10] PWM_X_GENA_ACTCMPBD_NONE Do nothing 0x0 PWM_X_GENA_ACTCMPBD_INV Invert pwmA 0x1 PWM_X_GENA_ACTCMPBD_ZERO Drive pwmA Low 0x2 PWM_X_GENA_ACTCMPBD_ONE Drive pwmA High 0x3 _0_GENB PWM0 Generator B Control 0x00000064 PWM_X_GENB_ACTZERO Action for Counter=0 [1:0] PWM_X_GENB_ACTZERO_NONE Do nothing 0x0 PWM_X_GENB_ACTZERO_INV Invert pwmB 0x1 PWM_X_GENB_ACTZERO_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTZERO_ONE Drive pwmB High 0x3 PWM_X_GENB_ACTLOAD Action for Counter=LOAD [3:2] PWM_X_GENB_ACTLOAD_NONE Do nothing 0x0 PWM_X_GENB_ACTLOAD_INV Invert pwmB 0x1 PWM_X_GENB_ACTLOAD_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTLOAD_ONE Drive pwmB High 0x3 PWM_X_GENB_ACTCMPAU Action for Comparator A Up [5:4] PWM_X_GENB_ACTCMPAU_NONE Do nothing 0x0 PWM_X_GENB_ACTCMPAU_INV Invert pwmB 0x1 PWM_X_GENB_ACTCMPAU_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTCMPAU_ONE Drive pwmB High 0x3 PWM_X_GENB_ACTCMPAD Action for Comparator A Down [7:6] PWM_X_GENB_ACTCMPAD_NONE Do nothing 0x0 PWM_X_GENB_ACTCMPAD_INV Invert pwmB 0x1 PWM_X_GENB_ACTCMPAD_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTCMPAD_ONE Drive pwmB High 0x3 PWM_X_GENB_ACTCMPBU Action for Comparator B Up [9:8] PWM_X_GENB_ACTCMPBU_NONE Do nothing 0x0 PWM_X_GENB_ACTCMPBU_INV Invert pwmB 0x1 PWM_X_GENB_ACTCMPBU_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTCMPBU_ONE Drive pwmB High 0x3 PWM_X_GENB_ACTCMPBD Action for Comparator B Down [11:10] PWM_X_GENB_ACTCMPBD_NONE Do nothing 0x0 PWM_X_GENB_ACTCMPBD_INV Invert pwmB 0x1 PWM_X_GENB_ACTCMPBD_ZERO Drive pwmB Low 0x2 PWM_X_GENB_ACTCMPBD_ONE Drive pwmB High 0x3 _0_DBCTL PWM0 Dead-Band Control 0x00000068 PWM_X_DBCTL_ENABLE Dead-Band Generator Enable [0:0] _0_DBRISE PWM0 Dead-Band Rising-Edge Delay 0x0000006C PWM_X_DBRISE_DELAY Dead-Band Rise Delay [11:0] _0_DBFALL PWM0 Dead-Band Falling-Edge-Delay 0x00000070 PWM_X_DBFALL_DELAY Dead-Band Fall Delay [11:0] _1_CTL PWM1 Control 0x00000080 _1_INTEN PWM1 Interrupt and Trigger Enable 0x00000084 _1_RIS PWM1 Raw Interrupt Status 0x00000088 _1_ISC PWM1 Interrupt Status and Clear 0x0000008C _1_LOAD PWM1 Load 0x00000090 _1_COUNT PWM1 Counter 0x00000094 _1_CMPA PWM1 Compare A 0x00000098 _1_CMPB PWM1 Compare B 0x0000009C _1_GENA PWM1 Generator A Control 0x000000A0 _1_GENB PWM1 Generator B Control 0x000000A4 _1_DBCTL PWM1 Dead-Band Control 0x000000A8 _1_DBRISE PWM1 Dead-Band Rising-Edge Delay 0x000000AC _1_DBFALL PWM1 Dead-Band Falling-Edge-Delay 0x000000B0 _2_CTL PWM2 Control 0x000000C0 _2_INTEN PWM2 Interrupt and Trigger Enable 0x000000C4 _2_RIS PWM2 Raw Interrupt Status 0x000000C8 _2_ISC PWM2 Interrupt Status and Clear 0x000000CC _2_LOAD PWM2 Load 0x000000D0 _2_COUNT PWM2 Counter 0x000000D4 _2_CMPA PWM2 Compare A 0x000000D8 _2_CMPB PWM2 Compare B 0x000000DC _2_GENA PWM2 Generator A Control 0x000000E0 _2_GENB PWM2 Generator B Control 0x000000E4 _2_DBCTL PWM2 Dead-Band Control 0x000000E8 _2_DBRISE PWM2 Dead-Band Rising-Edge Delay 0x000000EC _2_DBFALL PWM2 Dead-Band Falling-Edge-Delay 0x000000F0 QEI0 Register map for QEI0 peripheral QEI QEI0 0x4002C000 0 0x00001000 registers CTL QEI Control 0x00000000 QEI_CTL_ENABLE Enable QEI [0:0] QEI_CTL_SWAP Swap Signals [1:1] QEI_CTL_SIGMODE Signal Mode [2:2] QEI_CTL_CAPMODE Capture Mode [3:3] QEI_CTL_RESMODE Reset Mode [4:4] QEI_CTL_VELEN Capture Velocity [5:5] QEI_CTL_VELDIV Predivide Velocity [8:6] QEI_CTL_VELDIV_1 QEI clock /1 0x0 QEI_CTL_VELDIV_2 QEI clock /2 0x1 QEI_CTL_VELDIV_4 QEI clock /4 0x2 QEI_CTL_VELDIV_8 QEI clock /8 0x3 QEI_CTL_VELDIV_16 QEI clock /16 0x4 QEI_CTL_VELDIV_32 QEI clock /32 0x5 QEI_CTL_VELDIV_64 QEI clock /64 0x6 QEI_CTL_VELDIV_128 QEI clock /128 0x7 QEI_CTL_INVA Invert PhA [9:9] QEI_CTL_INVB Invert PhB [10:10] QEI_CTL_INVI Invert Index Pulse [11:11] QEI_CTL_STALLEN Stall QEI [12:12] STAT QEI Status 0x00000004 QEI_STAT_ERROR Error Detected [0:0] QEI_STAT_DIRECTION Direction of Rotation [1:1] POS QEI Position 0x00000008 QEI_POS Current Position Integrator Value [31:0] MAXPOS QEI Maximum Position 0x0000000C QEI_MAXPOS Maximum Position Integrator Value [31:0] LOAD QEI Timer Load 0x00000010 QEI_LOAD Velocity Timer Load Value [31:0] TIME QEI Timer 0x00000014 QEI_TIME Velocity Timer Current Value [31:0] COUNT QEI Velocity Counter 0x00000018 QEI_COUNT Velocity Pulse Count [31:0] SPEED QEI Velocity 0x0000001C QEI_SPEED Velocity [31:0] INTEN QEI Interrupt Enable 0x00000020 QEI_INTEN_INDEX Index Pulse Detected Interrupt Enable [0:0] QEI_INTEN_TIMER Timer Expires Interrupt Enable [1:1] QEI_INTEN_DIR Direction Change Interrupt Enable [2:2] QEI_INTEN_ERROR Phase Error Interrupt Enable [3:3] RIS QEI Raw Interrupt Status 0x00000024 QEI_RIS_INDEX Index Pulse Asserted [0:0] QEI_RIS_TIMER Velocity Timer Expired [1:1] QEI_RIS_DIR Direction Change Detected [2:2] QEI_RIS_ERROR Phase Error Detected [3:3] ISC QEI Interrupt Status and Clear 0x00000028 QEI_ISC_INDEX Index Pulse Interrupt [0:0] QEI_ISC_TIMER Velocity Timer Expired Interrupt [1:1] QEI_ISC_DIR Direction Change Interrupt [2:2] QEI_ISC_ERROR Phase Error Interrupt [3:3] QEI1 QEI1 0x4002D000 TIMER0 Register map for TIMER0 peripheral TIMER TIMER0 0x40030000 0 0x00001000 registers CFG GPTM Configuration 0x00000000 TIMER_CFG GPTM Configuration [2:0] TIMER_CFG_32_BIT_TIMER 32-bit timer configuration 0x0 TIMER_CFG_32_BIT_RTC 32-bit real-time clock (RTC) counter configuration 0x1 TIMER_CFG_16_BIT 16-bit timer configuration. The function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR 0x4 TAMR GPTM Timer A Mode 0x00000004 TIMER_TAMR_TAMR GPTM Timer A Mode [1:0] TIMER_TAMR_TAMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TAMR_TAMR_PERIOD Periodic Timer mode 0x2 TIMER_TAMR_TAMR_CAP Capture mode 0x3 TIMER_TAMR_TACMR GPTM Timer A Capture Mode [2:2] TIMER_TAMR_TAAMS GPTM Timer A Alternate Mode Select [3:3] TBMR GPTM Timer B Mode 0x00000008 TIMER_TBMR_TBMR GPTM Timer B Mode [1:0] TIMER_TBMR_TBMR_1_SHOT One-Shot Timer mode 0x1 TIMER_TBMR_TBMR_PERIOD Periodic Timer mode 0x2 TIMER_TBMR_TBMR_CAP Capture mode 0x3 TIMER_TBMR_TBCMR GPTM Timer B Capture Mode [2:2] TIMER_TBMR_TBAMS GPTM Timer B Alternate Mode Select [3:3] CTL GPTM Control 0x0000000C TIMER_CTL_TAEN GPTM Timer A Enable [0:0] TIMER_CTL_TASTALL GPTM Timer A Stall Enable [1:1] TIMER_CTL_TAEVENT GPTM Timer A Event Mode [3:2] TIMER_CTL_TAEVENT_POS Positive edge 0x0 TIMER_CTL_TAEVENT_NEG Negative edge 0x1 TIMER_CTL_TAEVENT_BOTH Both edges 0x3 TIMER_CTL_RTCEN GPTM RTC Enable [4:4] TIMER_CTL_TAOTE GPTM Timer A Output Trigger Enable [5:5] TIMER_CTL_TAPWML GPTM Timer A PWM Output Level [6:6] TIMER_CTL_TBEN GPTM Timer B Enable [8:8] TIMER_CTL_TBSTALL GPTM Timer B Stall Enable [9:9] TIMER_CTL_TBEVENT GPTM Timer B Event Mode [11:10] TIMER_CTL_TBEVENT_POS Positive edge 0x0 TIMER_CTL_TBEVENT_NEG Negative edge 0x1 TIMER_CTL_TBEVENT_BOTH Both edges 0x3 TIMER_CTL_TBOTE GPTM Timer B Output Trigger Enable [13:13] TIMER_CTL_TBPWML GPTM Timer B PWM Output Level [14:14] IMR GPTM Interrupt Mask 0x00000018 TIMER_IMR_TATOIM GPTM Timer A Time-Out Interrupt Mask [0:0] TIMER_IMR_CAMIM GPTM Capture A Match Interrupt Mask [1:1] TIMER_IMR_CAEIM GPTM Capture A Event Interrupt Mask [2:2] TIMER_IMR_RTCIM GPTM RTC Interrupt Mask [3:3] TIMER_IMR_TBTOIM GPTM Timer B Time-Out Interrupt Mask [8:8] TIMER_IMR_CBMIM GPTM Capture B Match Interrupt Mask [9:9] TIMER_IMR_CBEIM GPTM Capture B Event Interrupt Mask [10:10] RIS GPTM Raw Interrupt Status 0x0000001C TIMER_RIS_TATORIS GPTM Timer A Time-Out Raw Interrupt [0:0] TIMER_RIS_CAMRIS GPTM Capture A Match Raw Interrupt [1:1] TIMER_RIS_CAERIS GPTM Capture A Event Raw Interrupt [2:2] TIMER_RIS_RTCRIS GPTM RTC Raw Interrupt [3:3] TIMER_RIS_TBTORIS GPTM Timer B Time-Out Raw Interrupt [8:8] TIMER_RIS_CBMRIS GPTM Capture B Match Raw Interrupt [9:9] TIMER_RIS_CBERIS GPTM Capture B Event Raw Interrupt [10:10] MIS GPTM Masked Interrupt Status 0x00000020 TIMER_MIS_TATOMIS GPTM Timer A Time-Out Masked Interrupt [0:0] TIMER_MIS_CAMMIS GPTM Capture A Match Masked Interrupt [1:1] TIMER_MIS_CAEMIS GPTM Capture A Event Masked Interrupt [2:2] TIMER_MIS_RTCMIS GPTM RTC Masked Interrupt [3:3] TIMER_MIS_TBTOMIS GPTM Timer B Time-Out Masked Interrupt [8:8] TIMER_MIS_CBMMIS GPTM Capture B Match Masked Interrupt [9:9] TIMER_MIS_CBEMIS GPTM Capture B Event Masked Interrupt [10:10] ICR GPTM Interrupt Clear 0x00000024 write-only TIMER_ICR_TATOCINT GPTM Timer A Time-Out Raw Interrupt [0:0] write-only TIMER_ICR_CAMCINT GPTM Capture A Match Interrupt Clear [1:1] write-only TIMER_ICR_CAECINT GPTM Capture A Event Interrupt Clear [2:2] write-only TIMER_ICR_RTCCINT GPTM RTC Interrupt Clear [3:3] write-only TIMER_ICR_TBTOCINT GPTM Timer B Time-Out Interrupt Clear [8:8] write-only TIMER_ICR_CBMCINT GPTM Capture B Match Interrupt Clear [9:9] write-only TIMER_ICR_CBECINT GPTM Capture B Event Interrupt Clear [10:10] write-only TAILR GPTM Timer A Interval Load 0x00000028 TIMER_TAILR_TAILRL GPTM Timer A Interval Load Register Low [15:0] TIMER_TAILR_TAILRH GPTM Timer A Interval Load Register High [31:16] TBILR GPTM Timer B Interval Load 0x0000002C TIMER_TBILR_TBILRL GPTM Timer B Interval Load Register [15:0] TAMATCHR GPTM Timer A Match 0x00000030 TIMER_TAMATCHR_TAMRL GPTM Timer A Match Register Low [15:0] TIMER_TAMATCHR_TAMRH GPTM Timer A Match Register High [31:16] TBMATCHR GPTM Timer B Match 0x00000034 TIMER_TBMATCHR_TBMRL GPTM Timer B Match Register Low [15:0] TAPR GPTM Timer A Prescale 0x00000038 TIMER_TAPR_TAPSR GPTM Timer A Prescale [7:0] TBPR GPTM Timer B Prescale 0x0000003C TIMER_TBPR_TBPSR GPTM Timer B Prescale [7:0] TAPMR GPTM TimerA Prescale Match 0x00000040 TIMER_TAPMR_TAPSMR GPTM TimerA Prescale Match [7:0] TBPMR GPTM TimerB Prescale Match 0x00000044 TIMER_TBPMR_TBPSMR GPTM TimerB Prescale Match [7:0] TAR GPTM Timer A 0x00000048 TIMER_TAR_TARL GPTM Timer A Register Low [15:0] TIMER_TAR_TARH GPTM Timer A Register High [31:16] TBR GPTM Timer B 0x0000004C TIMER_TBR_TBRL GPTM Timer B [15:0] TIMER1 TIMER1 0x40031000 TIMER2 TIMER2 0x40032000 TIMER3 TIMER3 0x40033000 ADC0 Register map for ADC0 peripheral ADC ADC0 0x40038000 0 0x00001000 registers ACTSS ADC Active Sample Sequencer 0x00000000 ADC_ACTSS_ASEN0 ADC SS0 Enable [0:0] ADC_ACTSS_ASEN1 ADC SS1 Enable [1:1] ADC_ACTSS_ASEN2 ADC SS2 Enable [2:2] ADC_ACTSS_ASEN3 ADC SS3 Enable [3:3] RIS ADC Raw Interrupt Status 0x00000004 ADC_RIS_INR0 SS0 Raw Interrupt Status [0:0] ADC_RIS_INR1 SS1 Raw Interrupt Status [1:1] ADC_RIS_INR2 SS2 Raw Interrupt Status [2:2] ADC_RIS_INR3 SS3 Raw Interrupt Status [3:3] IM ADC Interrupt Mask 0x00000008 ADC_IM_MASK0 SS0 Interrupt Mask [0:0] ADC_IM_MASK1 SS1 Interrupt Mask [1:1] ADC_IM_MASK2 SS2 Interrupt Mask [2:2] ADC_IM_MASK3 SS3 Interrupt Mask [3:3] ISC ADC Interrupt Status and Clear 0x0000000C ADC_ISC_IN0 SS0 Interrupt Status and Clear [0:0] ADC_ISC_IN1 SS1 Interrupt Status and Clear [1:1] ADC_ISC_IN2 SS2 Interrupt Status and Clear [2:2] ADC_ISC_IN3 SS3 Interrupt Status and Clear [3:3] OSTAT ADC Overflow Status 0x00000010 ADC_OSTAT_OV0 SS0 FIFO Overflow [0:0] ADC_OSTAT_OV1 SS1 FIFO Overflow [1:1] ADC_OSTAT_OV2 SS2 FIFO Overflow [2:2] ADC_OSTAT_OV3 SS3 FIFO Overflow [3:3] EMUX ADC Event Multiplexer Select 0x00000014 ADC_EMUX_EM0 SS0 Trigger Select [3:0] ADC_EMUX_EM0_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM0_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM0_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM0_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM0_TIMER Timer 0x5 ADC_EMUX_EM0_PWM0 PWM0 0x6 ADC_EMUX_EM0_PWM1 PWM1 0x7 ADC_EMUX_EM0_PWM2 PWM2 0x8 ADC_EMUX_EM0_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM1 SS1 Trigger Select [7:4] ADC_EMUX_EM1_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM1_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM1_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM1_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM1_TIMER Timer 0x5 ADC_EMUX_EM1_PWM0 PWM0 0x6 ADC_EMUX_EM1_PWM1 PWM1 0x7 ADC_EMUX_EM1_PWM2 PWM2 0x8 ADC_EMUX_EM1_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM2 SS2 Trigger Select [11:8] ADC_EMUX_EM2_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM2_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM2_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM2_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM2_TIMER Timer 0x5 ADC_EMUX_EM2_PWM0 PWM0 0x6 ADC_EMUX_EM2_PWM1 PWM1 0x7 ADC_EMUX_EM2_PWM2 PWM2 0x8 ADC_EMUX_EM2_ALWAYS Always (continuously sample) 0xf ADC_EMUX_EM3 SS3 Trigger Select [15:12] ADC_EMUX_EM3_PROCESSOR Processor (default) 0x0 ADC_EMUX_EM3_COMP0 Analog Comparator 0 0x1 ADC_EMUX_EM3_COMP1 Analog Comparator 1 0x2 ADC_EMUX_EM3_EXTERNAL External (GPIO PB4) 0x4 ADC_EMUX_EM3_TIMER Timer 0x5 ADC_EMUX_EM3_PWM0 PWM0 0x6 ADC_EMUX_EM3_PWM1 PWM1 0x7 ADC_EMUX_EM3_PWM2 PWM2 0x8 ADC_EMUX_EM3_ALWAYS Always (continuously sample) 0xf USTAT ADC Underflow Status 0x00000018 ADC_USTAT_UV0 SS0 FIFO Underflow [0:0] ADC_USTAT_UV1 SS1 FIFO Underflow [1:1] ADC_USTAT_UV2 SS2 FIFO Underflow [2:2] ADC_USTAT_UV3 SS3 FIFO Underflow [3:3] SSPRI ADC Sample Sequencer Priority 0x00000020 ADC_SSPRI_SS0 SS0 Priority [1:0] ADC_SSPRI_SS0_1ST First priority 0x0 ADC_SSPRI_SS0_2ND Second priority 0x1 ADC_SSPRI_SS0_3RD Third priority 0x2 ADC_SSPRI_SS0_4TH Fourth priority 0x3 ADC_SSPRI_SS1 SS1 Priority [5:4] ADC_SSPRI_SS1_1ST First priority 0x0 ADC_SSPRI_SS1_2ND Second priority 0x1 ADC_SSPRI_SS1_3RD Third priority 0x2 ADC_SSPRI_SS1_4TH Fourth priority 0x3 ADC_SSPRI_SS2 SS2 Priority [9:8] ADC_SSPRI_SS2_1ST First priority 0x0 ADC_SSPRI_SS2_2ND Second priority 0x1 ADC_SSPRI_SS2_3RD Third priority 0x2 ADC_SSPRI_SS2_4TH Fourth priority 0x3 ADC_SSPRI_SS3 SS3 Priority [13:12] ADC_SSPRI_SS3_1ST First priority 0x0 ADC_SSPRI_SS3_2ND Second priority 0x1 ADC_SSPRI_SS3_3RD Third priority 0x2 ADC_SSPRI_SS3_4TH Fourth priority 0x3 PSSI ADC Processor Sample Sequence Initiate 0x00000028 ADC_PSSI_SS0 SS0 Initiate [0:0] ADC_PSSI_SS1 SS1 Initiate [1:1] ADC_PSSI_SS2 SS2 Initiate [2:2] ADC_PSSI_SS3 SS3 Initiate [3:3] SAC ADC Sample Averaging Control 0x00000030 ADC_SAC_AVG Hardware Averaging Control [2:0] ADC_SAC_AVG_OFF No hardware oversampling 0x0 ADC_SAC_AVG_2X 2x hardware oversampling 0x1 ADC_SAC_AVG_4X 4x hardware oversampling 0x2 ADC_SAC_AVG_8X 8x hardware oversampling 0x3 ADC_SAC_AVG_16X 16x hardware oversampling 0x4 ADC_SAC_AVG_32X 32x hardware oversampling 0x5 ADC_SAC_AVG_64X 64x hardware oversampling 0x6 SSMUX0 ADC Sample Sequence Input Multiplexer Select 0 0x00000040 ADC_SSMUX0_MUX0 1st Sample Input Select [1:0] ADC_SSMUX0_MUX1 2nd Sample Input Select [5:4] ADC_SSMUX0_MUX2 3rd Sample Input Select [9:8] ADC_SSMUX0_MUX3 4th Sample Input Select [13:12] ADC_SSMUX0_MUX4 5th Sample Input Select [17:16] ADC_SSMUX0_MUX5 6th Sample Input Select [21:20] ADC_SSMUX0_MUX6 7th Sample Input Select [25:24] ADC_SSMUX0_MUX7 8th Sample Input Select [29:28] SSCTL0 ADC Sample Sequence Control 0 0x00000044 ADC_SSCTL0_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL0_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL0_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL0_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL0_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL0_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL0_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL0_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL0_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL0_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL0_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL0_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL0_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL0_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL0_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL0_TS3 4th Sample Temp Sensor Select [15:15] ADC_SSCTL0_D4 5th Sample Diff Input Select [16:16] ADC_SSCTL0_END4 5th Sample is End of Sequence [17:17] ADC_SSCTL0_IE4 5th Sample Interrupt Enable [18:18] ADC_SSCTL0_TS4 5th Sample Temp Sensor Select [19:19] ADC_SSCTL0_D5 6th Sample Diff Input Select [20:20] ADC_SSCTL0_END5 6th Sample is End of Sequence [21:21] ADC_SSCTL0_IE5 6th Sample Interrupt Enable [22:22] ADC_SSCTL0_TS5 6th Sample Temp Sensor Select [23:23] ADC_SSCTL0_D6 7th Sample Diff Input Select [24:24] ADC_SSCTL0_END6 7th Sample is End of Sequence [25:25] ADC_SSCTL0_IE6 7th Sample Interrupt Enable [26:26] ADC_SSCTL0_TS6 7th Sample Temp Sensor Select [27:27] ADC_SSCTL0_D7 8th Sample Diff Input Select [28:28] ADC_SSCTL0_END7 8th Sample is End of Sequence [29:29] ADC_SSCTL0_IE7 8th Sample Interrupt Enable [30:30] ADC_SSCTL0_TS7 8th Sample Temp Sensor Select [31:31] SSFIFO0 ADC Sample Sequence Result FIFO 0 0x00000048 ADC_SSFIFO0_DATA Conversion Result Data [9:0] SSFSTAT0 ADC Sample Sequence FIFO 0 Status 0x0000004C ADC_SSFSTAT0_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT0_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT0_EMPTY FIFO Empty [8:8] ADC_SSFSTAT0_FULL FIFO Full [12:12] SSMUX1 ADC Sample Sequence Input Multiplexer Select 1 0x00000060 ADC_SSMUX1_MUX0 1st Sample Input Select [1:0] ADC_SSMUX1_MUX1 2nd Sample Input Select [5:4] ADC_SSMUX1_MUX2 3rd Sample Input Select [9:8] ADC_SSMUX1_MUX3 4th Sample Input Select [13:12] SSCTL1 ADC Sample Sequence Control 1 0x00000064 ADC_SSCTL1_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL1_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL1_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL1_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL1_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL1_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL1_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL1_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL1_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL1_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL1_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL1_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL1_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL1_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL1_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL1_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO1 ADC Sample Sequence Result FIFO 1 0x00000068 ADC_SSFIFO1_DATA Conversion Result Data [9:0] SSFSTAT1 ADC Sample Sequence FIFO 1 Status 0x0000006C ADC_SSFSTAT1_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT1_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT1_EMPTY FIFO Empty [8:8] ADC_SSFSTAT1_FULL FIFO Full [12:12] SSMUX2 ADC Sample Sequence Input Multiplexer Select 2 0x00000080 ADC_SSMUX2_MUX0 1st Sample Input Select [1:0] ADC_SSMUX2_MUX1 2nd Sample Input Select [5:4] ADC_SSMUX2_MUX2 3rd Sample Input Select [9:8] ADC_SSMUX2_MUX3 4th Sample Input Select [13:12] SSCTL2 ADC Sample Sequence Control 2 0x00000084 ADC_SSCTL2_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL2_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL2_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL2_TS0 1st Sample Temp Sensor Select [3:3] ADC_SSCTL2_D1 2nd Sample Diff Input Select [4:4] ADC_SSCTL2_END1 2nd Sample is End of Sequence [5:5] ADC_SSCTL2_IE1 2nd Sample Interrupt Enable [6:6] ADC_SSCTL2_TS1 2nd Sample Temp Sensor Select [7:7] ADC_SSCTL2_D2 3rd Sample Diff Input Select [8:8] ADC_SSCTL2_END2 3rd Sample is End of Sequence [9:9] ADC_SSCTL2_IE2 3rd Sample Interrupt Enable [10:10] ADC_SSCTL2_TS2 3rd Sample Temp Sensor Select [11:11] ADC_SSCTL2_D3 4th Sample Diff Input Select [12:12] ADC_SSCTL2_END3 4th Sample is End of Sequence [13:13] ADC_SSCTL2_IE3 4th Sample Interrupt Enable [14:14] ADC_SSCTL2_TS3 4th Sample Temp Sensor Select [15:15] SSFIFO2 ADC Sample Sequence Result FIFO 2 0x00000088 ADC_SSFIFO2_DATA Conversion Result Data [9:0] SSFSTAT2 ADC Sample Sequence FIFO 2 Status 0x0000008C ADC_SSFSTAT2_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT2_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT2_EMPTY FIFO Empty [8:8] ADC_SSFSTAT2_FULL FIFO Full [12:12] SSMUX3 ADC Sample Sequence Input Multiplexer Select 3 0x000000A0 ADC_SSMUX3_MUX0 1st Sample Input Select [1:0] SSCTL3 ADC Sample Sequence Control 3 0x000000A4 ADC_SSCTL3_D0 1st Sample Diff Input Select [0:0] ADC_SSCTL3_END0 1st Sample is End of Sequence [1:1] ADC_SSCTL3_IE0 1st Sample Interrupt Enable [2:2] ADC_SSCTL3_TS0 1st Sample Temp Sensor Select [3:3] SSFIFO3 ADC Sample Sequence Result FIFO 3 0x000000A8 ADC_SSFIFO3_DATA Conversion Result Data [9:0] SSFSTAT3 ADC Sample Sequence FIFO 3 Status 0x000000AC ADC_SSFSTAT3_TPTR FIFO Tail Pointer [3:0] ADC_SSFSTAT3_HPTR FIFO Head Pointer [7:4] ADC_SSFSTAT3_EMPTY FIFO Empty [8:8] ADC_SSFSTAT3_FULL FIFO Full [12:12] TMLB ADC Test Mode Loopback 0x00000100 ADC_TMLB_LB Loopback Mode Enable [0:0] COMP Register map for COMP peripheral COMP COMP 0x4003C000 0 0x00001000 registers ACMIS Analog Comparator Masked Interrupt Status 0x00000000 COMP_ACMIS_IN0 Comparator 0 Masked Interrupt Status [0:0] COMP_ACMIS_IN1 Comparator 1 Masked Interrupt Status [1:1] ACRIS Analog Comparator Raw Interrupt Status 0x00000004 COMP_ACRIS_IN0 Comparator 0 Interrupt Status [0:0] COMP_ACRIS_IN1 Comparator 1 Interrupt Status [1:1] ACINTEN Analog Comparator Interrupt Enable 0x00000008 COMP_ACINTEN_IN0 Comparator 0 Interrupt Enable [0:0] COMP_ACINTEN_IN1 Comparator 1 Interrupt Enable [1:1] ACREFCTL Analog Comparator Reference Voltage Control 0x00000010 COMP_ACREFCTL_VREF Resistor Ladder Voltage Ref [3:0] COMP_ACREFCTL_RNG Resistor Ladder Range [8:8] COMP_ACREFCTL_EN Resistor Ladder Enable [9:9] ACSTAT0 Analog Comparator Status 0 0x00000020 COMP_ACSTAT0_OVAL Comparator Output Value [1:1] ACCTL0 Analog Comparator Control 0 0x00000024 COMP_ACCTL0_CINV Comparator Output Invert [1:1] COMP_ACCTL0_ISEN Interrupt Sense [3:2] COMP_ACCTL0_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL0_ISEN_FALL Falling edge 0x1 COMP_ACCTL0_ISEN_RISE Rising edge 0x2 COMP_ACCTL0_ISEN_BOTH Either edge 0x3 COMP_ACCTL0_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL0_TSEN Trigger Sense [6:5] COMP_ACCTL0_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL0_TSEN_FALL Falling edge 0x1 COMP_ACCTL0_TSEN_RISE Rising edge 0x2 COMP_ACCTL0_TSEN_BOTH Either edge 0x3 COMP_ACCTL0_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL0_ASRCP Analog Source Positive [10:9] COMP_ACCTL0_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL0_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL0_ASRCP_REF Internal voltage reference (VIREF) 0x2 COMP_ACCTL0_TOEN Trigger Output Enable [11:11] ACSTAT1 Analog Comparator Status 1 0x00000040 COMP_ACSTAT1_OVAL Comparator Output Value [1:1] ACCTL1 Analog Comparator Control 1 0x00000044 COMP_ACCTL1_CINV Comparator Output Invert [1:1] COMP_ACCTL1_ISEN Interrupt Sense [3:2] COMP_ACCTL1_ISEN_LEVEL Level sense, see ISLVAL 0x0 COMP_ACCTL1_ISEN_FALL Falling edge 0x1 COMP_ACCTL1_ISEN_RISE Rising edge 0x2 COMP_ACCTL1_ISEN_BOTH Either edge 0x3 COMP_ACCTL1_ISLVAL Interrupt Sense Level Value [4:4] COMP_ACCTL1_TSEN Trigger Sense [6:5] COMP_ACCTL1_TSEN_LEVEL Level sense, see TSLVAL 0x0 COMP_ACCTL1_TSEN_FALL Falling edge 0x1 COMP_ACCTL1_TSEN_RISE Rising edge 0x2 COMP_ACCTL1_TSEN_BOTH Either edge 0x3 COMP_ACCTL1_TSLVAL Trigger Sense Level Value [7:7] COMP_ACCTL1_ASRCP Analog Source Positive [10:9] COMP_ACCTL1_ASRCP_PIN Pin value of Cn+ 0x0 COMP_ACCTL1_ASRCP_PIN0 Pin value of C0+ 0x1 COMP_ACCTL1_ASRCP_REF Internal voltage reference (VIREF) 0x2 COMP_ACCTL1_TOEN Trigger Output Enable [11:11] MAC Register map for MAC peripheral MAC MAC 0x40048000 0 0x00001000 registers RIS Ethernet MAC Raw Interrupt Status/Acknowledge 0x00000000 MAC_RIS_RXINT Packet Received [0:0] MAC_RIS_TXER Transmit Error [1:1] MAC_RIS_TXEMP Transmit FIFO Empty [2:2] MAC_RIS_FOV FIFO Overrun [3:3] MAC_RIS_RXER Receive Error [4:4] MAC_RIS_MDINT MII Transaction Complete [5:5] MAC_RIS_PHYINT PHY Interrupt [6:6] IACK Ethernet MAC Raw Interrupt Status/Acknowledge MAC_ALT 0x00000000 MAC_IACK_RXINT Clear Packet Received [0:0] MAC_IACK_TXER Clear Transmit Error [1:1] MAC_IACK_TXEMP Clear Transmit FIFO Empty [2:2] MAC_IACK_FOV Clear FIFO Overrun [3:3] MAC_IACK_RXER Clear Receive Error [4:4] MAC_IACK_MDINT Clear MII Transaction Complete [5:5] MAC_IACK_PHYINT Clear PHY Interrupt [6:6] IM Ethernet MAC Interrupt Mask 0x00000004 MAC_IM_RXINTM Mask Packet Received [0:0] MAC_IM_TXERM Mask Transmit Error [1:1] MAC_IM_TXEMPM Mask Transmit FIFO Empty [2:2] MAC_IM_FOVM Mask FIFO Overrun [3:3] MAC_IM_RXERM Mask Receive Error [4:4] MAC_IM_MDINTM Mask MII Transaction Complete [5:5] MAC_IM_PHYINTM Mask PHY Interrupt [6:6] RCTL Ethernet MAC Receive Control 0x00000008 MAC_RCTL_RXEN Enable Receiver [0:0] MAC_RCTL_AMUL Enable Multicast Frames [1:1] MAC_RCTL_PRMS Enable Promiscuous Mode [2:2] MAC_RCTL_BADCRC Enable Reject Bad CRC [3:3] MAC_RCTL_RSTFIFO Clear Receive FIFO [4:4] TCTL Ethernet MAC Transmit Control 0x0000000C MAC_TCTL_TXEN Enable Transmitter [0:0] MAC_TCTL_PADEN Enable Packet Padding [1:1] MAC_TCTL_CRC Enable CRC Generation [2:2] MAC_TCTL_DUPLEX Enable Duplex Mode [4:4] DATA Ethernet MAC Data 0x00000010 MAC_DATA_RXDATA Receive FIFO Data [31:0] DATA Ethernet MAC Data MAC_ALT 0x00000010 MAC_DATA_TXDATA Transmit FIFO Data [31:0] IA0 Ethernet MAC Individual Address 0 0x00000014 MAC_IA0_MACOCT1 MAC Address Octet 1 [7:0] MAC_IA0_MACOCT2 MAC Address Octet 2 [15:8] MAC_IA0_MACOCT3 MAC Address Octet 3 [23:16] MAC_IA0_MACOCT4 MAC Address Octet 4 [31:24] IA1 Ethernet MAC Individual Address 1 0x00000018 MAC_IA1_MACOCT5 MAC Address Octet 5 [7:0] MAC_IA1_MACOCT6 MAC Address Octet 6 [15:8] THR Ethernet MAC Threshold 0x0000001C MAC_THR_THRESH Threshold Value [5:0] MCTL Ethernet MAC Management Control 0x00000020 MAC_MCTL_START MII Register Transaction Enable [0:0] MAC_MCTL_WRITE MII Register Transaction Type [1:1] MAC_MCTL_REGADR MII Register Address [7:3] MDV Ethernet MAC Management Divider 0x00000024 MAC_MDV_DIV Clock Divider [7:0] MTXD Ethernet MAC Management Transmit Data 0x0000002C MAC_MTXD_MDTX MII Register Transmit Data [15:0] MRXD Ethernet MAC Management Receive Data 0x00000030 MAC_MRXD_MDRX MII Register Receive Data [15:0] NP Ethernet MAC Number of Packets 0x00000034 MAC_NP_NPR Number of Packets in Receive FIFO [5:0] TR Ethernet MAC Transmission Request 0x00000038 MAC_TR_NEWTX New Transmission [0:0] HIB Register map for HIB peripheral HIB HIB 0x400FC000 0 0x00001000 registers RTCC Hibernation RTC Counter 0x00000000 HIB_RTCC RTC Counter [31:0] RTCM0 Hibernation RTC Match 0 0x00000004 HIB_RTCM0 RTC Match 0 [31:0] RTCM1 Hibernation RTC Match 1 0x00000008 HIB_RTCM1 RTC Match 1 [31:0] RTCLD Hibernation RTC Load 0x0000000C HIB_RTCLD RTC Load [31:0] CTL Hibernation Control 0x00000010 HIB_CTL_RTCEN RTC Timer Enable [0:0] HIB_CTL_HIBREQ Hibernation Request [1:1] HIB_CTL_CLKSEL Hibernation Module Clock Select [2:2] HIB_CTL_RTCWEN RTC Wake-up Enable [3:3] HIB_CTL_PINWEN External WAKE Pin Enable [4:4] HIB_CTL_LOWBATEN Low Battery Monitoring Enable [5:5] HIB_CTL_CLK32EN Clocking Enable [6:6] HIB_CTL_VABORT Power Cut Abort Enable [7:7] IM Hibernation Interrupt Mask 0x00000014 HIB_IM_RTCALT0 RTC Alert 0 Interrupt Mask [0:0] HIB_IM_RTCALT1 RTC Alert 1 Interrupt Mask [1:1] HIB_IM_LOWBAT Low Battery Voltage Interrupt Mask [2:2] HIB_IM_EXTW External Wake-Up Interrupt Mask [3:3] RIS Hibernation Raw Interrupt Status 0x00000018 HIB_RIS_RTCALT0 RTC Alert 0 Raw Interrupt Status [0:0] HIB_RIS_RTCALT1 RTC Alert 1 Raw Interrupt Status [1:1] HIB_RIS_LOWBAT Low Battery Voltage Raw Interrupt Status [2:2] HIB_RIS_EXTW External Wake-Up Raw Interrupt Status [3:3] MIS Hibernation Masked Interrupt Status 0x0000001C HIB_MIS_RTCALT0 RTC Alert 0 Masked Interrupt Status [0:0] HIB_MIS_RTCALT1 RTC Alert 1 Masked Interrupt Status [1:1] HIB_MIS_LOWBAT Low Battery Voltage Masked Interrupt Status [2:2] HIB_MIS_EXTW External Wake-Up Masked Interrupt Status [3:3] IC Hibernation Interrupt Clear 0x00000020 HIB_IC_RTCALT0 RTC Alert0 Masked Interrupt Clear [0:0] HIB_IC_RTCALT1 RTC Alert1 Masked Interrupt Clear [1:1] HIB_IC_LOWBAT Low Battery Voltage Masked Interrupt Clear [2:2] HIB_IC_EXTW External Wake-Up Masked Interrupt Clear [3:3] RTCT Hibernation RTC Trim 0x00000024 HIB_RTCT_TRIM RTC Trim Value [15:0] DATA Hibernation Data 0x00000030 HIB_DATA_RTD Hibernation Module NV Data [31:0] FLASH_CTRL Register map for FLASH_CTRL peripheral FLASH_CTRL FLASH_CTRL 0x400FD000 0 0x00001000 registers 0x1000 0x00001000 registers FMA Flash Memory Address 0x00000000 FLASH_FMA_OFFSET Address Offset [17:0] FMD Flash Memory Data 0x00000004 FLASH_FMD_DATA Data Value [31:0] FMC Flash Memory Control 0x00000008 FLASH_FMC_WRITE Write a Word into Flash Memory [0:0] FLASH_FMC_ERASE Erase a Page of Flash Memory [1:1] FLASH_FMC_MERASE Mass Erase Flash Memory [2:2] FLASH_FMC_COMT Commit Register Value [3:3] FLASH_FMC_WRKEY FLASH write key [31:17] FCRIS Flash Controller Raw Interrupt Status 0x0000000C FLASH_FCRIS_ARIS Access Raw Interrupt Status [0:0] FLASH_FCRIS_PRIS Programming Raw Interrupt Status [1:1] FCIM Flash Controller Interrupt Mask 0x00000010 FLASH_FCIM_AMASK Access Interrupt Mask [0:0] FLASH_FCIM_PMASK Programming Interrupt Mask [1:1] FCMISC Flash Controller Masked Interrupt Status and Clear 0x00000014 FLASH_FCMISC_AMISC Access Masked Interrupt Status and Clear [0:0] FLASH_FCMISC_PMISC Programming Masked Interrupt Status and Clear [1:1] USECRL USec Reload 0x00001140 FLASH_USECRL Microsecond Reload Value [7:0] USERDBG User Debug FLASH_ALT 0x000011D0 FLASH_USERDBG_DBG0 Debug Control 0 [0:0] FLASH_USERDBG_DBG1 Debug Control 1 [1:1] FLASH_USERDBG_DATA User Data [30:2] FLASH_USERDBG_NW User Debug Not Written [31:31] USERREG0 User Register 0 0x000011E0 FLASH_USERREG0_DATA User Data [30:0] FLASH_USERREG0_NW Not Written [31:31] USERREG1 User Register 1 0x000011E4 FLASH_USERREG1_DATA User Data [30:0] FLASH_USERREG1_NW Not Written [31:31] FMPRE0 Flash Memory Protection Read Enable 0 0x00001200 FMPRE1 Flash Memory Protection Read Enable 1 0x00001204 FMPRE2 Flash Memory Protection Read Enable 2 0x00001208 FMPRE3 Flash Memory Protection Read Enable 3 0x0000120C FMPPE0 Flash Memory Protection Program Enable 0 0x00001400 FMPPE1 Flash Memory Protection Program Enable 1 0x00001404 FMPPE2 Flash Memory Protection Program Enable 2 0x00001408 FMPPE3 Flash Memory Protection Program Enable 3 0x0000140C SYSCTL Register map for SYSCTL peripheral SYSCTL SYSCTL 0x400FE000 0 0x00001000 registers DID0 Device Identification 0 0x00000000 SYSCTL_DID0_MIN Minor Revision [7:0] SYSCTL_DID0_MIN_0 Initial device, or a major revision update 0x0 SYSCTL_DID0_MIN_1 First metal layer change 0x1 SYSCTL_DID0_MIN_2 Second metal layer change 0x2 SYSCTL_DID0_MAJ Major Revision [15:8] SYSCTL_DID0_MAJ_REVA Revision A (initial device) 0x0 SYSCTL_DID0_MAJ_REVB Revision B (first base layer revision) 0x1 SYSCTL_DID0_MAJ_REVC Revision C (second base layer revision) 0x2 SYSCTL_DID0_CLASS Device Class [23:16] SYSCTL_DID0_CLASS_FURY Stellaris(R) Fury-class devices 0x1 SYSCTL_DID0_VER DID0 Version [30:28] SYSCTL_DID0_VER_1 Second version of the DID0 register format 0x1 DID1 Device Identification 1 0x00000004 SYSCTL_DID1_QUAL Qualification Status [1:0] SYSCTL_DID1_QUAL_ES Engineering Sample (unqualified) 0x0 SYSCTL_DID1_QUAL_PP Pilot Production (unqualified) 0x1 SYSCTL_DID1_QUAL_FQ Fully Qualified 0x2 SYSCTL_DID1_ROHS RoHS-Compliance [2:2] SYSCTL_DID1_PKG Package Type [4:3] SYSCTL_DID1_PKG_SOIC SOIC package 0x0 SYSCTL_DID1_PKG_QFP LQFP package 0x1 SYSCTL_DID1_PKG_BGA BGA package 0x2 SYSCTL_DID1_TEMP Temperature Range [7:5] SYSCTL_DID1_TEMP_C Commercial temperature range (0C to 70C) 0x0 SYSCTL_DID1_TEMP_I Industrial temperature range (-40C to 85C) 0x1 SYSCTL_DID1_TEMP_E Extended temperature range (-40C to 105C) 0x2 SYSCTL_DID1_PINCNT Package Pin Count [15:13] SYSCTL_DID1_PINCNT_100 100-pin package 0x2 SYSCTL_DID1_PRTNO Part Number [23:16] SYSCTL_DID1_PRTNO_6965 LM3S6965 0x73 SYSCTL_DID1_FAM Family [27:24] SYSCTL_DID1_FAM_STELLARIS Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S 0x0 SYSCTL_DID1_VER DID1 Version [31:28] SYSCTL_DID1_VER_1 Second version of the DID1 register format 0x1 DC0 Device Capabilities 0 0x00000008 SYSCTL_DC0_FLASHSZ Flash Size [15:0] SYSCTL_DC0_FLASHSZ_256K 256 KB of Flash 0x7f SYSCTL_DC0_SRAMSZ SRAM Size [31:16] SYSCTL_DC0_SRAMSZ_64KB 64 KB of SRAM 0xff DC1 Device Capabilities 1 0x00000010 SYSCTL_DC1_JTAG JTAG Present [0:0] SYSCTL_DC1_SWD SWD Present [1:1] SYSCTL_DC1_SWO SWO Trace Port Present [2:2] SYSCTL_DC1_WDT0 Watchdog Timer 0 Present [3:3] SYSCTL_DC1_PLL PLL Present [4:4] SYSCTL_DC1_TEMP Temp Sensor Present [5:5] SYSCTL_DC1_HIB Hibernation Module Present [6:6] SYSCTL_DC1_MPU MPU Present [7:7] SYSCTL_DC1_MINSYSDIV System Clock Divider [15:12] SYSCTL_DC1_MINSYSDIV_50 Specifies a 50-MHz CPU clock with a PLL divider of 4 0x3 DC2 Device Capabilities 2 0x00000014 SYSCTL_DC2_UART0 UART Module 0 Present [0:0] SYSCTL_DC2_UART1 UART Module 1 Present [1:1] SYSCTL_DC2_UART2 UART Module 2 Present [2:2] SYSCTL_DC2_SSI0 SSI Module 0 Present [4:4] SYSCTL_DC2_QEI0 QEI Module 0 Present [8:8] SYSCTL_DC2_QEI1 QEI Module 1 Present [9:9] SYSCTL_DC2_I2C0 I2C Module 0 Present [12:12] SYSCTL_DC2_I2C1 I2C Module 1 Present [14:14] SYSCTL_DC2_TIMER0 Timer Module 0 Present [16:16] SYSCTL_DC2_TIMER1 Timer Module 1 Present [17:17] SYSCTL_DC2_TIMER2 Timer Module 2 Present [18:18] SYSCTL_DC2_TIMER3 Timer Module 3 Present [19:19] SYSCTL_DC2_COMP0 Analog Comparator 0 Present [24:24] SYSCTL_DC2_COMP1 Analog Comparator 1 Present [25:25] DC3 Device Capabilities 3 0x00000018 SYSCTL_DC3_PWM0 PWM0 Pin Present [0:0] SYSCTL_DC3_PWM1 PWM1 Pin Present [1:1] SYSCTL_DC3_PWM2 PWM2 Pin Present [2:2] SYSCTL_DC3_PWM3 PWM3 Pin Present [3:3] SYSCTL_DC3_PWM4 PWM4 Pin Present [4:4] SYSCTL_DC3_PWM5 PWM5 Pin Present [5:5] SYSCTL_DC3_C0MINUS C0- Pin Present [6:6] SYSCTL_DC3_C0PLUS C0+ Pin Present [7:7] SYSCTL_DC3_C0O C0o Pin Present [8:8] SYSCTL_DC3_C1MINUS C1- Pin Present [9:9] SYSCTL_DC3_C1PLUS C1+ Pin Present [10:10] SYSCTL_DC3_PWMFAULT PWM Fault Pin Present [15:15] SYSCTL_DC3_CCP0 CCP0 Pin Present [24:24] SYSCTL_DC3_CCP1 CCP1 Pin Present [25:25] SYSCTL_DC3_CCP2 CCP2 Pin Present [26:26] SYSCTL_DC3_CCP3 CCP3 Pin Present [27:27] SYSCTL_DC3_32KHZ 32KHz Input Clock Available [31:31] DC4 Device Capabilities 4 0x0000001C SYSCTL_DC4_GPIOA GPIO Port A Present [0:0] SYSCTL_DC4_GPIOB GPIO Port B Present [1:1] SYSCTL_DC4_GPIOC GPIO Port C Present [2:2] SYSCTL_DC4_GPIOD GPIO Port D Present [3:3] SYSCTL_DC4_GPIOE GPIO Port E Present [4:4] SYSCTL_DC4_GPIOF GPIO Port F Present [5:5] SYSCTL_DC4_GPIOG GPIO Port G Present [6:6] SYSCTL_DC4_EMAC0 Ethernet MAC Layer 0 Present [28:28] SYSCTL_DC4_EPHY0 Ethernet PHY Layer 0 Present [30:30] PBORCTL Brown-Out Reset Control 0x00000030 SYSCTL_PBORCTL_BORIOR BOR Interrupt or Reset [1:1] LDOPCTL LDO Power Control 0x00000034 SYSCTL_LDOPCTL LDO Output Voltage [5:0] SYSCTL_LDOPCTL_2_50V 2.50 0x0 SYSCTL_LDOPCTL_2_45V 2.45 0x1 SYSCTL_LDOPCTL_2_40V 2.40 0x2 SYSCTL_LDOPCTL_2_35V 2.35 0x3 SYSCTL_LDOPCTL_2_30V 2.30 0x4 SYSCTL_LDOPCTL_2_25V 2.25 0x5 SYSCTL_LDOPCTL_2_75V 2.75 0x1b SYSCTL_LDOPCTL_2_70V 2.70 0x1c SYSCTL_LDOPCTL_2_65V 2.65 0x1d SYSCTL_LDOPCTL_2_60V 2.60 0x1e SYSCTL_LDOPCTL_2_55V 2.55 0x1f SRCR0 Software Reset Control 0 0x00000040 SYSCTL_SRCR0_HIB HIB Reset Control [6:6] SRCR1 Software Reset Control 1 0x00000044 SYSCTL_SRCR1_UART0 UART0 Reset Control [0:0] SYSCTL_SRCR1_UART1 UART1 Reset Control [1:1] SYSCTL_SRCR1_UART2 UART2 Reset Control [2:2] SYSCTL_SRCR1_SSI0 SSI0 Reset Control [4:4] SYSCTL_SRCR1_QEI0 QEI0 Reset Control [8:8] SYSCTL_SRCR1_QEI1 QEI1 Reset Control [9:9] SYSCTL_SRCR1_I2C0 I2C0 Reset Control [12:12] SYSCTL_SRCR1_I2C1 I2C1 Reset Control [14:14] SYSCTL_SRCR1_TIMER0 Timer 0 Reset Control [16:16] SYSCTL_SRCR1_TIMER1 Timer 1 Reset Control [17:17] SYSCTL_SRCR1_TIMER2 Timer 2 Reset Control [18:18] SYSCTL_SRCR1_TIMER3 Timer 3 Reset Control [19:19] SYSCTL_SRCR1_COMP0 Analog Comp 0 Reset Control [24:24] SYSCTL_SRCR1_COMP1 Analog Comp 1 Reset Control [25:25] SRCR2 Software Reset Control 2 0x00000048 SYSCTL_SRCR2_GPIOA Port A Reset Control [0:0] SYSCTL_SRCR2_GPIOB Port B Reset Control [1:1] SYSCTL_SRCR2_GPIOC Port C Reset Control [2:2] SYSCTL_SRCR2_GPIOD Port D Reset Control [3:3] SYSCTL_SRCR2_GPIOE Port E Reset Control [4:4] SYSCTL_SRCR2_GPIOF Port F Reset Control [5:5] SYSCTL_SRCR2_GPIOG Port G Reset Control [6:6] SYSCTL_SRCR2_EMAC0 MAC0 Reset Control [28:28] SYSCTL_SRCR2_EPHY0 PHY0 Reset Control [30:30] RIS Raw Interrupt Status 0x00000050 SYSCTL_RIS_BORRIS Brown-Out Reset Raw Interrupt Status [1:1] SYSCTL_RIS_PLLLRIS PLL Lock Raw Interrupt Status [6:6] IMC Interrupt Mask Control 0x00000054 SYSCTL_IMC_BORIM Brown-Out Reset Interrupt Mask [1:1] SYSCTL_IMC_PLLLIM PLL Lock Interrupt Mask [6:6] MISC Masked Interrupt Status and Clear 0x00000058 SYSCTL_MISC_BORMIS BOR Masked Interrupt Status [1:1] SYSCTL_MISC_PLLLMIS PLL Lock Masked Interrupt Status [6:6] RESC Reset Cause 0x0000005C SYSCTL_RESC_EXT External Reset [0:0] SYSCTL_RESC_POR Power-On Reset [1:1] SYSCTL_RESC_BOR Brown-Out Reset [2:2] SYSCTL_RESC_SW Software Reset [4:4] RCC Run-Mode Clock Configuration 0x00000060 SYSCTL_RCC_MOSCDIS Main Oscillator Disable [0:0] SYSCTL_RCC_IOSCDIS Internal Oscillator Disable [1:1] SYSCTL_RCC_OSCSRC Oscillator Source [5:4] SYSCTL_RCC_OSCSRC_MAIN MOSC 0x0 SYSCTL_RCC_OSCSRC_INT IOSC 0x1 SYSCTL_RCC_OSCSRC_INT4 IOSC/4 0x2 SYSCTL_RCC_OSCSRC_30 30 kHz 0x3 SYSCTL_RCC_XTAL Crystal Value [9:6] SYSCTL_RCC_XTAL_1MHZ 1 MHz 0x0 SYSCTL_RCC_XTAL_1_84MHZ 1.8432 MHz 0x1 SYSCTL_RCC_XTAL_2MHZ 2 MHz 0x2 SYSCTL_RCC_XTAL_2_45MHZ 2.4576 MHz 0x3 SYSCTL_RCC_XTAL_3_57MHZ 3.579545 MHz 0x4 SYSCTL_RCC_XTAL_3_68MHZ 3.6864 MHz 0x5 SYSCTL_RCC_XTAL_4MHZ 4 MHz 0x6 SYSCTL_RCC_XTAL_4_09MHZ 4.096 MHz 0x7 SYSCTL_RCC_XTAL_4_91MHZ 4.9152 MHz 0x8 SYSCTL_RCC_XTAL_5MHZ 5 MHz 0x9 SYSCTL_RCC_XTAL_5_12MHZ 5.12 MHz 0xa SYSCTL_RCC_XTAL_6MHZ 6 MHz 0xb SYSCTL_RCC_XTAL_6_14MHZ 6.144 MHz 0xc SYSCTL_RCC_XTAL_7_37MHZ 7.3728 MHz 0xd SYSCTL_RCC_XTAL_8MHZ 8 MHz 0xe SYSCTL_RCC_XTAL_8_19MHZ 8.192 MHz 0xf SYSCTL_RCC_BYPASS PLL Bypass [11:11] SYSCTL_RCC_PWRDN PLL Power Down [13:13] SYSCTL_RCC_PWMDIV PWM Unit Clock Divisor [19:17] SYSCTL_RCC_PWMDIV_2 PWM clock /2 0x0 SYSCTL_RCC_PWMDIV_4 PWM clock /4 0x1 SYSCTL_RCC_PWMDIV_8 PWM clock /8 0x2 SYSCTL_RCC_PWMDIV_16 PWM clock /16 0x3 SYSCTL_RCC_PWMDIV_32 PWM clock /32 0x4 SYSCTL_RCC_PWMDIV_64 PWM clock /64 0x5 SYSCTL_RCC_USEPWMDIV Enable PWM Clock Divisor [20:20] SYSCTL_RCC_USESYSDIV Enable System Clock Divider [22:22] SYSCTL_RCC_SYSDIV System Clock Divisor [26:23] SYSCTL_RCC_SYSDIV_2 System clock /2 0x1 SYSCTL_RCC_SYSDIV_3 System clock /3 0x2 SYSCTL_RCC_SYSDIV_4 System clock /4 0x3 SYSCTL_RCC_SYSDIV_5 System clock /5 0x4 SYSCTL_RCC_SYSDIV_6 System clock /6 0x5 SYSCTL_RCC_SYSDIV_7 System clock /7 0x6 SYSCTL_RCC_SYSDIV_8 System clock /8 0x7 SYSCTL_RCC_SYSDIV_9 System clock /9 0x8 SYSCTL_RCC_SYSDIV_10 System clock /10 0x9 SYSCTL_RCC_SYSDIV_11 System clock /11 0xa SYSCTL_RCC_SYSDIV_12 System clock /12 0xb SYSCTL_RCC_SYSDIV_13 System clock /13 0xc SYSCTL_RCC_SYSDIV_14 System clock /14 0xd SYSCTL_RCC_SYSDIV_15 System clock /15 0xe SYSCTL_RCC_SYSDIV_16 System clock /16 0xf SYSCTL_RCC_ACG Auto Clock Gating [27:27] PLLCFG XTAL to PLL Translation 0x00000064 SYSCTL_PLLCFG_R PLL R Value [4:0] SYSCTL_PLLCFG_F PLL F Value [13:5] RCC2 Run-Mode Clock Configuration 2 0x00000070 SYSCTL_RCC2_OSCSRC2 Oscillator Source 2 [6:4] SYSCTL_RCC2_OSCSRC2_MO MOSC 0x0 SYSCTL_RCC2_OSCSRC2_IO PIOSC 0x1 SYSCTL_RCC2_OSCSRC2_IO4 PIOSC/4 0x2 SYSCTL_RCC2_OSCSRC2_30 30 kHz 0x3 SYSCTL_RCC2_OSCSRC2_32 32.768 kHz 0x7 SYSCTL_RCC2_BYPASS2 PLL Bypass 2 [11:11] SYSCTL_RCC2_PWRDN2 Power-Down PLL 2 [13:13] SYSCTL_RCC2_SYSDIV2 System Clock Divisor 2 [28:23] SYSCTL_RCC2_SYSDIV2_2 System clock /2 0x1 SYSCTL_RCC2_SYSDIV2_3 System clock /3 0x2 SYSCTL_RCC2_SYSDIV2_4 System clock /4 0x3 SYSCTL_RCC2_SYSDIV2_5 System clock /5 0x4 SYSCTL_RCC2_SYSDIV2_6 System clock /6 0x5 SYSCTL_RCC2_SYSDIV2_7 System clock /7 0x6 SYSCTL_RCC2_SYSDIV2_8 System clock /8 0x7 SYSCTL_RCC2_SYSDIV2_9 System clock /9 0x8 SYSCTL_RCC2_SYSDIV2_10 System clock /10 0x9 SYSCTL_RCC2_SYSDIV2_11 System clock /11 0xa SYSCTL_RCC2_SYSDIV2_12 System clock /12 0xb SYSCTL_RCC2_SYSDIV2_13 System clock /13 0xc SYSCTL_RCC2_SYSDIV2_14 System clock /14 0xd SYSCTL_RCC2_SYSDIV2_15 System clock /15 0xe SYSCTL_RCC2_SYSDIV2_16 System clock /16 0xf SYSCTL_RCC2_SYSDIV2_17 System clock /17 0x10 SYSCTL_RCC2_SYSDIV2_18 System clock /18 0x11 SYSCTL_RCC2_SYSDIV2_19 System clock /19 0x12 SYSCTL_RCC2_SYSDIV2_20 System clock /20 0x13 SYSCTL_RCC2_SYSDIV2_21 System clock /21 0x14 SYSCTL_RCC2_SYSDIV2_22 System clock /22 0x15 SYSCTL_RCC2_SYSDIV2_23 System clock /23 0x16 SYSCTL_RCC2_SYSDIV2_24 System clock /24 0x17 SYSCTL_RCC2_SYSDIV2_25 System clock /25 0x18 SYSCTL_RCC2_SYSDIV2_26 System clock /26 0x19 SYSCTL_RCC2_SYSDIV2_27 System clock /27 0x1a SYSCTL_RCC2_SYSDIV2_28 System clock /28 0x1b SYSCTL_RCC2_SYSDIV2_29 System clock /29 0x1c SYSCTL_RCC2_SYSDIV2_30 System clock /30 0x1d SYSCTL_RCC2_SYSDIV2_31 System clock /31 0x1e SYSCTL_RCC2_SYSDIV2_32 System clock /32 0x1f SYSCTL_RCC2_SYSDIV2_33 System clock /33 0x20 SYSCTL_RCC2_SYSDIV2_34 System clock /34 0x21 SYSCTL_RCC2_SYSDIV2_35 System clock /35 0x22 SYSCTL_RCC2_SYSDIV2_36 System clock /36 0x23 SYSCTL_RCC2_SYSDIV2_37 System clock /37 0x24 SYSCTL_RCC2_SYSDIV2_38 System clock /38 0x25 SYSCTL_RCC2_SYSDIV2_39 System clock /39 0x26 SYSCTL_RCC2_SYSDIV2_40 System clock /40 0x27 SYSCTL_RCC2_SYSDIV2_41 System clock /41 0x28 SYSCTL_RCC2_SYSDIV2_42 System clock /42 0x29 SYSCTL_RCC2_SYSDIV2_43 System clock /43 0x2a SYSCTL_RCC2_SYSDIV2_44 System clock /44 0x2b SYSCTL_RCC2_SYSDIV2_45 System clock /45 0x2c SYSCTL_RCC2_SYSDIV2_46 System clock /46 0x2d SYSCTL_RCC2_SYSDIV2_47 System clock /47 0x2e SYSCTL_RCC2_SYSDIV2_48 System clock /48 0x2f SYSCTL_RCC2_SYSDIV2_49 System clock /49 0x30 SYSCTL_RCC2_SYSDIV2_50 System clock /50 0x31 SYSCTL_RCC2_SYSDIV2_51 System clock /51 0x32 SYSCTL_RCC2_SYSDIV2_52 System clock /52 0x33 SYSCTL_RCC2_SYSDIV2_53 System clock /53 0x34 SYSCTL_RCC2_SYSDIV2_54 System clock /54 0x35 SYSCTL_RCC2_SYSDIV2_55 System clock /55 0x36 SYSCTL_RCC2_SYSDIV2_56 System clock /56 0x37 SYSCTL_RCC2_SYSDIV2_57 System clock /57 0x38 SYSCTL_RCC2_SYSDIV2_58 System clock /58 0x39 SYSCTL_RCC2_SYSDIV2_59 System clock /59 0x3a SYSCTL_RCC2_SYSDIV2_60 System clock /60 0x3b SYSCTL_RCC2_SYSDIV2_61 System clock /61 0x3c SYSCTL_RCC2_SYSDIV2_62 System clock /62 0x3d SYSCTL_RCC2_SYSDIV2_63 System clock /63 0x3e SYSCTL_RCC2_SYSDIV2_64 System clock /64 0x3f SYSCTL_RCC2_USERCC2 Use RCC2 [31:31] RCGC0 Run Mode Clock Gating Control Register 0 0x00000100 SYSCTL_RCGC0_HIB HIB Clock Gating Control [6:6] SYSCTL_RCGC0_ADCSPD ADC Sample Speed [9:8] SYSCTL_RCGC0_ADCSPD125K 125K samples/second 0x0 SYSCTL_RCGC0_ADCSPD250K 250K samples/second 0x1 SYSCTL_RCGC0_ADCSPD500K 500K samples/second 0x2 SYSCTL_RCGC0_ADCSPD1M 1M samples/second 0x3 RCGC1 Run Mode Clock Gating Control Register 1 0x00000104 SYSCTL_RCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_RCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_RCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_RCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_RCGC1_QEI0 QEI0 Clock Gating Control [8:8] SYSCTL_RCGC1_QEI1 QEI1 Clock Gating Control [9:9] SYSCTL_RCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_RCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_RCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_RCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_RCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_RCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_RCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_RCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] RCGC2 Run Mode Clock Gating Control Register 2 0x00000108 SYSCTL_RCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_RCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_RCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_RCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_RCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_RCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_RCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_RCGC2_EMAC0 MAC0 Clock Gating Control [28:28] SYSCTL_RCGC2_EPHY0 PHY0 Clock Gating Control [30:30] SCGC0 Sleep Mode Clock Gating Control Register 0 0x00000110 SYSCTL_SCGC0_HIB HIB Clock Gating Control [6:6] SYSCTL_SCGC0_ADCSPD ADC Sample Speed [9:8] SYSCTL_SCGC0_ADCSPD125K 125K samples/second 0x0 SYSCTL_SCGC0_ADCSPD250K 250K samples/second 0x1 SYSCTL_SCGC0_ADCSPD500K 500K samples/second 0x2 SYSCTL_SCGC0_ADCSPD1M 1M samples/second 0x3 SCGC1 Sleep Mode Clock Gating Control Register 1 0x00000114 SYSCTL_SCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_SCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_SCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_SCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_SCGC1_QEI0 QEI0 Clock Gating Control [8:8] SYSCTL_SCGC1_QEI1 QEI1 Clock Gating Control [9:9] SYSCTL_SCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_SCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_SCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_SCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_SCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_SCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_SCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_SCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] SCGC2 Sleep Mode Clock Gating Control Register 2 0x00000118 SYSCTL_SCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_SCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_SCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_SCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_SCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_SCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_SCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_SCGC2_EMAC0 MAC0 Clock Gating Control [28:28] SYSCTL_SCGC2_EPHY0 PHY0 Clock Gating Control [30:30] DCGC0 Deep Sleep Mode Clock Gating Control Register 0 0x00000120 SYSCTL_DCGC0_HIB HIB Clock Gating Control [6:6] DCGC1 Deep-Sleep Mode Clock Gating Control Register 1 0x00000124 SYSCTL_DCGC1_UART0 UART0 Clock Gating Control [0:0] SYSCTL_DCGC1_UART1 UART1 Clock Gating Control [1:1] SYSCTL_DCGC1_UART2 UART2 Clock Gating Control [2:2] SYSCTL_DCGC1_SSI0 SSI0 Clock Gating Control [4:4] SYSCTL_DCGC1_QEI0 QEI0 Clock Gating Control [8:8] SYSCTL_DCGC1_QEI1 QEI1 Clock Gating Control [9:9] SYSCTL_DCGC1_I2C0 I2C0 Clock Gating Control [12:12] SYSCTL_DCGC1_I2C1 I2C1 Clock Gating Control [14:14] SYSCTL_DCGC1_TIMER0 Timer 0 Clock Gating Control [16:16] SYSCTL_DCGC1_TIMER1 Timer 1 Clock Gating Control [17:17] SYSCTL_DCGC1_TIMER2 Timer 2 Clock Gating Control [18:18] SYSCTL_DCGC1_TIMER3 Timer 3 Clock Gating Control [19:19] SYSCTL_DCGC1_COMP0 Analog Comparator 0 Clock Gating [24:24] SYSCTL_DCGC1_COMP1 Analog Comparator 1 Clock Gating [25:25] DCGC2 Deep Sleep Mode Clock Gating Control Register 2 0x00000128 SYSCTL_DCGC2_GPIOA Port A Clock Gating Control [0:0] SYSCTL_DCGC2_GPIOB Port B Clock Gating Control [1:1] SYSCTL_DCGC2_GPIOC Port C Clock Gating Control [2:2] SYSCTL_DCGC2_GPIOD Port D Clock Gating Control [3:3] SYSCTL_DCGC2_GPIOE Port E Clock Gating Control [4:4] SYSCTL_DCGC2_GPIOF Port F Clock Gating Control [5:5] SYSCTL_DCGC2_GPIOG Port G Clock Gating Control [6:6] SYSCTL_DCGC2_EMAC0 MAC0 Clock Gating Control [28:28] SYSCTL_DCGC2_EPHY0 PHY0 Clock Gating Control [30:30] DSLPCLKCFG Deep Sleep Clock Configuration 0x00000144 SYSCTL_DSLPCLKCFG_O Clock Source [6:4] SYSCTL_DSLPCLKCFG_O_IGN MOSC 0x0 SYSCTL_DSLPCLKCFG_O_IO PIOSC 0x1 SYSCTL_DSLPCLKCFG_O_30 30 kHz 0x3 SYSCTL_DSLPCLKCFG_O_32 32.768 kHz 0x7 SYSCTL_DSLPCLKCFG_D Divider Field Override [28:23] SYSCTL_DSLPCLKCFG_D_1 System clock /1 0x0 SYSCTL_DSLPCLKCFG_D_2 System clock /2 0x1 SYSCTL_DSLPCLKCFG_D_3 System clock /3 0x2 SYSCTL_DSLPCLKCFG_D_4 System clock /4 0x3 SYSCTL_DSLPCLKCFG_D_5 System clock /5 0x4 SYSCTL_DSLPCLKCFG_D_6 System clock /6 0x5 SYSCTL_DSLPCLKCFG_D_7 System clock /7 0x6 SYSCTL_DSLPCLKCFG_D_8 System clock /8 0x7 SYSCTL_DSLPCLKCFG_D_9 System clock /9 0x8 SYSCTL_DSLPCLKCFG_D_10 System clock /10 0x9 SYSCTL_DSLPCLKCFG_D_11 System clock /11 0xa SYSCTL_DSLPCLKCFG_D_12 System clock /12 0xb SYSCTL_DSLPCLKCFG_D_13 System clock /13 0xc SYSCTL_DSLPCLKCFG_D_14 System clock /14 0xd SYSCTL_DSLPCLKCFG_D_15 System clock /15 0xe SYSCTL_DSLPCLKCFG_D_16 System clock /16 0xf SYSCTL_DSLPCLKCFG_D_17 System clock /17 0x10 SYSCTL_DSLPCLKCFG_D_18 System clock /18 0x11 SYSCTL_DSLPCLKCFG_D_19 System clock /19 0x12 SYSCTL_DSLPCLKCFG_D_20 System clock /20 0x13 SYSCTL_DSLPCLKCFG_D_21 System clock /21 0x14 SYSCTL_DSLPCLKCFG_D_22 System clock /22 0x15 SYSCTL_DSLPCLKCFG_D_23 System clock /23 0x16 SYSCTL_DSLPCLKCFG_D_24 System clock /24 0x17 SYSCTL_DSLPCLKCFG_D_25 System clock /25 0x18 SYSCTL_DSLPCLKCFG_D_26 System clock /26 0x19 SYSCTL_DSLPCLKCFG_D_27 System clock /27 0x1a SYSCTL_DSLPCLKCFG_D_28 System clock /28 0x1b SYSCTL_DSLPCLKCFG_D_29 System clock /29 0x1c SYSCTL_DSLPCLKCFG_D_30 System clock /30 0x1d SYSCTL_DSLPCLKCFG_D_31 System clock /31 0x1e SYSCTL_DSLPCLKCFG_D_32 System clock /32 0x1f SYSCTL_DSLPCLKCFG_D_33 System clock /33 0x20 SYSCTL_DSLPCLKCFG_D_34 System clock /34 0x21 SYSCTL_DSLPCLKCFG_D_35 System clock /35 0x22 SYSCTL_DSLPCLKCFG_D_36 System clock /36 0x23 SYSCTL_DSLPCLKCFG_D_37 System clock /37 0x24 SYSCTL_DSLPCLKCFG_D_38 System clock /38 0x25 SYSCTL_DSLPCLKCFG_D_39 System clock /39 0x26 SYSCTL_DSLPCLKCFG_D_40 System clock /40 0x27 SYSCTL_DSLPCLKCFG_D_41 System clock /41 0x28 SYSCTL_DSLPCLKCFG_D_42 System clock /42 0x29 SYSCTL_DSLPCLKCFG_D_43 System clock /43 0x2a SYSCTL_DSLPCLKCFG_D_44 System clock /44 0x2b SYSCTL_DSLPCLKCFG_D_45 System clock /45 0x2c SYSCTL_DSLPCLKCFG_D_46 System clock /46 0x2d SYSCTL_DSLPCLKCFG_D_47 System clock /47 0x2e SYSCTL_DSLPCLKCFG_D_48 System clock /48 0x2f SYSCTL_DSLPCLKCFG_D_49 System clock /49 0x30 SYSCTL_DSLPCLKCFG_D_50 System clock /50 0x31 SYSCTL_DSLPCLKCFG_D_51 System clock /51 0x32 SYSCTL_DSLPCLKCFG_D_52 System clock /52 0x33 SYSCTL_DSLPCLKCFG_D_53 System clock /53 0x34 SYSCTL_DSLPCLKCFG_D_54 System clock /54 0x35 SYSCTL_DSLPCLKCFG_D_55 System clock /55 0x36 SYSCTL_DSLPCLKCFG_D_56 System clock /56 0x37 SYSCTL_DSLPCLKCFG_D_57 System clock /57 0x38 SYSCTL_DSLPCLKCFG_D_58 System clock /58 0x39 SYSCTL_DSLPCLKCFG_D_59 System clock /59 0x3a SYSCTL_DSLPCLKCFG_D_60 System clock /60 0x3b SYSCTL_DSLPCLKCFG_D_61 System clock /61 0x3c SYSCTL_DSLPCLKCFG_D_62 System clock /62 0x3d SYSCTL_DSLPCLKCFG_D_63 System clock /63 0x3e SYSCTL_DSLPCLKCFG_D_64 System clock /64 0x3f NVIC Register map for NVIC peripheral NVIC NVIC 0xE000E000 0 0x00001000 registers INT_TYPE Interrupt Controller Type Reg 0x00000004 NVIC_INT_TYPE_LINES Number of interrupt lines (x32) [4:0] ST_CTRL SysTick Control and Status Register 0x00000010 NVIC_ST_CTRL_ENABLE Enable [0:0] NVIC_ST_CTRL_INTEN Interrupt Enable [1:1] NVIC_ST_CTRL_CLK_SRC Clock Source [2:2] NVIC_ST_CTRL_COUNT Count Flag [16:16] ST_RELOAD SysTick Reload Value Register 0x00000014 NVIC_ST_RELOAD Reload Value [23:0] ST_CURRENT SysTick Current Value Register 0x00000018 NVIC_ST_CURRENT Current Value [23:0] ST_CAL SysTick Calibration Value Reg 0x0000001C NVIC_ST_CAL_ONEMS 1ms reference value [23:0] NVIC_ST_CAL_SKEW Clock skew [30:30] NVIC_ST_CAL_NOREF No reference clock [31:31] EN0 Interrupt 0-31 Set Enable 0x00000100 NVIC_EN0_INT Interrupt Enable [31:0] NVIC_EN0_INT0 Interrupt 0 enable 0x1 NVIC_EN0_INT1 Interrupt 1 enable 0x2 NVIC_EN0_INT2 Interrupt 2 enable 0x4 NVIC_EN0_INT3 Interrupt 3 enable 0x8 NVIC_EN0_INT4 Interrupt 4 enable 0x10 NVIC_EN0_INT5 Interrupt 5 enable 0x20 NVIC_EN0_INT6 Interrupt 6 enable 0x40 NVIC_EN0_INT7 Interrupt 7 enable 0x80 NVIC_EN0_INT8 Interrupt 8 enable 0x100 NVIC_EN0_INT9 Interrupt 9 enable 0x200 NVIC_EN0_INT10 Interrupt 10 enable 0x400 NVIC_EN0_INT11 Interrupt 11 enable 0x800 NVIC_EN0_INT12 Interrupt 12 enable 0x1000 NVIC_EN0_INT13 Interrupt 13 enable 0x2000 NVIC_EN0_INT14 Interrupt 14 enable 0x4000 NVIC_EN0_INT15 Interrupt 15 enable 0x8000 NVIC_EN0_INT16 Interrupt 16 enable 0x10000 NVIC_EN0_INT17 Interrupt 17 enable 0x20000 NVIC_EN0_INT18 Interrupt 18 enable 0x40000 NVIC_EN0_INT19 Interrupt 19 enable 0x80000 NVIC_EN0_INT20 Interrupt 20 enable 0x100000 NVIC_EN0_INT21 Interrupt 21 enable 0x200000 NVIC_EN0_INT22 Interrupt 22 enable 0x400000 NVIC_EN0_INT23 Interrupt 23 enable 0x800000 NVIC_EN0_INT24 Interrupt 24 enable 0x1000000 NVIC_EN0_INT25 Interrupt 25 enable 0x2000000 NVIC_EN0_INT26 Interrupt 26 enable 0x4000000 NVIC_EN0_INT27 Interrupt 27 enable 0x8000000 NVIC_EN0_INT28 Interrupt 28 enable 0x10000000 NVIC_EN0_INT29 Interrupt 29 enable 0x20000000 NVIC_EN0_INT30 Interrupt 30 enable 0x40000000 NVIC_EN0_INT31 Interrupt 31 enable 0x80000000 EN1 Interrupt 32-54 Set Enable 0x00000104 NVIC_EN1_INT Interrupt Enable [11:0] NVIC_EN1_INT32 Interrupt 32 enable 0x1 NVIC_EN1_INT33 Interrupt 33 enable 0x2 NVIC_EN1_INT34 Interrupt 34 enable 0x4 NVIC_EN1_INT35 Interrupt 35 enable 0x8 NVIC_EN1_INT36 Interrupt 36 enable 0x10 NVIC_EN1_INT37 Interrupt 37 enable 0x20 NVIC_EN1_INT38 Interrupt 38 enable 0x40 NVIC_EN1_INT39 Interrupt 39 enable 0x80 NVIC_EN1_INT40 Interrupt 40 enable 0x100 NVIC_EN1_INT41 Interrupt 41 enable 0x200 NVIC_EN1_INT42 Interrupt 42 enable 0x400 NVIC_EN1_INT43 Interrupt 43 enable 0x800 DIS0 Interrupt 0-31 Clear Enable 0x00000180 NVIC_DIS0_INT Interrupt Disable [31:0] NVIC_DIS0_INT0 Interrupt 0 disable 0x1 NVIC_DIS0_INT1 Interrupt 1 disable 0x2 NVIC_DIS0_INT2 Interrupt 2 disable 0x4 NVIC_DIS0_INT3 Interrupt 3 disable 0x8 NVIC_DIS0_INT4 Interrupt 4 disable 0x10 NVIC_DIS0_INT5 Interrupt 5 disable 0x20 NVIC_DIS0_INT6 Interrupt 6 disable 0x40 NVIC_DIS0_INT7 Interrupt 7 disable 0x80 NVIC_DIS0_INT8 Interrupt 8 disable 0x100 NVIC_DIS0_INT9 Interrupt 9 disable 0x200 NVIC_DIS0_INT10 Interrupt 10 disable 0x400 NVIC_DIS0_INT11 Interrupt 11 disable 0x800 NVIC_DIS0_INT12 Interrupt 12 disable 0x1000 NVIC_DIS0_INT13 Interrupt 13 disable 0x2000 NVIC_DIS0_INT14 Interrupt 14 disable 0x4000 NVIC_DIS0_INT15 Interrupt 15 disable 0x8000 NVIC_DIS0_INT16 Interrupt 16 disable 0x10000 NVIC_DIS0_INT17 Interrupt 17 disable 0x20000 NVIC_DIS0_INT18 Interrupt 18 disable 0x40000 NVIC_DIS0_INT19 Interrupt 19 disable 0x80000 NVIC_DIS0_INT20 Interrupt 20 disable 0x100000 NVIC_DIS0_INT21 Interrupt 21 disable 0x200000 NVIC_DIS0_INT22 Interrupt 22 disable 0x400000 NVIC_DIS0_INT23 Interrupt 23 disable 0x800000 NVIC_DIS0_INT24 Interrupt 24 disable 0x1000000 NVIC_DIS0_INT25 Interrupt 25 disable 0x2000000 NVIC_DIS0_INT26 Interrupt 26 disable 0x4000000 NVIC_DIS0_INT27 Interrupt 27 disable 0x8000000 NVIC_DIS0_INT28 Interrupt 28 disable 0x10000000 NVIC_DIS0_INT29 Interrupt 29 disable 0x20000000 NVIC_DIS0_INT30 Interrupt 30 disable 0x40000000 NVIC_DIS0_INT31 Interrupt 31 disable 0x80000000 DIS1 Interrupt 32-54 Clear Enable 0x00000184 NVIC_DIS1_INT Interrupt Disable [11:0] NVIC_DIS1_INT32 Interrupt 32 disable 0x1 NVIC_DIS1_INT33 Interrupt 33 disable 0x2 NVIC_DIS1_INT34 Interrupt 34 disable 0x4 NVIC_DIS1_INT35 Interrupt 35 disable 0x8 NVIC_DIS1_INT36 Interrupt 36 disable 0x10 NVIC_DIS1_INT37 Interrupt 37 disable 0x20 NVIC_DIS1_INT38 Interrupt 38 disable 0x40 NVIC_DIS1_INT39 Interrupt 39 disable 0x80 NVIC_DIS1_INT40 Interrupt 40 disable 0x100 NVIC_DIS1_INT41 Interrupt 41 disable 0x200 NVIC_DIS1_INT42 Interrupt 42 disable 0x400 NVIC_DIS1_INT43 Interrupt 43 disable 0x800 PEND0 Interrupt 0-31 Set Pending 0x00000200 NVIC_PEND0_INT Interrupt Set Pending [31:0] NVIC_PEND0_INT0 Interrupt 0 pend 0x1 NVIC_PEND0_INT1 Interrupt 1 pend 0x2 NVIC_PEND0_INT2 Interrupt 2 pend 0x4 NVIC_PEND0_INT3 Interrupt 3 pend 0x8 NVIC_PEND0_INT4 Interrupt 4 pend 0x10 NVIC_PEND0_INT5 Interrupt 5 pend 0x20 NVIC_PEND0_INT6 Interrupt 6 pend 0x40 NVIC_PEND0_INT7 Interrupt 7 pend 0x80 NVIC_PEND0_INT8 Interrupt 8 pend 0x100 NVIC_PEND0_INT9 Interrupt 9 pend 0x200 NVIC_PEND0_INT10 Interrupt 10 pend 0x400 NVIC_PEND0_INT11 Interrupt 11 pend 0x800 NVIC_PEND0_INT12 Interrupt 12 pend 0x1000 NVIC_PEND0_INT13 Interrupt 13 pend 0x2000 NVIC_PEND0_INT14 Interrupt 14 pend 0x4000 NVIC_PEND0_INT15 Interrupt 15 pend 0x8000 NVIC_PEND0_INT16 Interrupt 16 pend 0x10000 NVIC_PEND0_INT17 Interrupt 17 pend 0x20000 NVIC_PEND0_INT18 Interrupt 18 pend 0x40000 NVIC_PEND0_INT19 Interrupt 19 pend 0x80000 NVIC_PEND0_INT20 Interrupt 20 pend 0x100000 NVIC_PEND0_INT21 Interrupt 21 pend 0x200000 NVIC_PEND0_INT22 Interrupt 22 pend 0x400000 NVIC_PEND0_INT23 Interrupt 23 pend 0x800000 NVIC_PEND0_INT24 Interrupt 24 pend 0x1000000 NVIC_PEND0_INT25 Interrupt 25 pend 0x2000000 NVIC_PEND0_INT26 Interrupt 26 pend 0x4000000 NVIC_PEND0_INT27 Interrupt 27 pend 0x8000000 NVIC_PEND0_INT28 Interrupt 28 pend 0x10000000 NVIC_PEND0_INT29 Interrupt 29 pend 0x20000000 NVIC_PEND0_INT30 Interrupt 30 pend 0x40000000 NVIC_PEND0_INT31 Interrupt 31 pend 0x80000000 PEND1 Interrupt 32-54 Set Pending 0x00000204 NVIC_PEND1_INT Interrupt Set Pending [11:0] NVIC_PEND1_INT32 Interrupt 32 pend 0x1 NVIC_PEND1_INT33 Interrupt 33 pend 0x2 NVIC_PEND1_INT34 Interrupt 34 pend 0x4 NVIC_PEND1_INT35 Interrupt 35 pend 0x8 NVIC_PEND1_INT36 Interrupt 36 pend 0x10 NVIC_PEND1_INT37 Interrupt 37 pend 0x20 NVIC_PEND1_INT38 Interrupt 38 pend 0x40 NVIC_PEND1_INT39 Interrupt 39 pend 0x80 NVIC_PEND1_INT40 Interrupt 40 pend 0x100 NVIC_PEND1_INT41 Interrupt 41 pend 0x200 NVIC_PEND1_INT42 Interrupt 42 pend 0x400 NVIC_PEND1_INT43 Interrupt 43 pend 0x800 UNPEND0 Interrupt 0-31 Clear Pending 0x00000280 NVIC_UNPEND0_INT Interrupt Clear Pending [31:0] NVIC_UNPEND0_INT0 Interrupt 0 unpend 0x1 NVIC_UNPEND0_INT1 Interrupt 1 unpend 0x2 NVIC_UNPEND0_INT2 Interrupt 2 unpend 0x4 NVIC_UNPEND0_INT3 Interrupt 3 unpend 0x8 NVIC_UNPEND0_INT4 Interrupt 4 unpend 0x10 NVIC_UNPEND0_INT5 Interrupt 5 unpend 0x20 NVIC_UNPEND0_INT6 Interrupt 6 unpend 0x40 NVIC_UNPEND0_INT7 Interrupt 7 unpend 0x80 NVIC_UNPEND0_INT8 Interrupt 8 unpend 0x100 NVIC_UNPEND0_INT9 Interrupt 9 unpend 0x200 NVIC_UNPEND0_INT10 Interrupt 10 unpend 0x400 NVIC_UNPEND0_INT11 Interrupt 11 unpend 0x800 NVIC_UNPEND0_INT12 Interrupt 12 unpend 0x1000 NVIC_UNPEND0_INT13 Interrupt 13 unpend 0x2000 NVIC_UNPEND0_INT14 Interrupt 14 unpend 0x4000 NVIC_UNPEND0_INT15 Interrupt 15 unpend 0x8000 NVIC_UNPEND0_INT16 Interrupt 16 unpend 0x10000 NVIC_UNPEND0_INT17 Interrupt 17 unpend 0x20000 NVIC_UNPEND0_INT18 Interrupt 18 unpend 0x40000 NVIC_UNPEND0_INT19 Interrupt 19 unpend 0x80000 NVIC_UNPEND0_INT20 Interrupt 20 unpend 0x100000 NVIC_UNPEND0_INT21 Interrupt 21 unpend 0x200000 NVIC_UNPEND0_INT22 Interrupt 22 unpend 0x400000 NVIC_UNPEND0_INT23 Interrupt 23 unpend 0x800000 NVIC_UNPEND0_INT24 Interrupt 24 unpend 0x1000000 NVIC_UNPEND0_INT25 Interrupt 25 unpend 0x2000000 NVIC_UNPEND0_INT26 Interrupt 26 unpend 0x4000000 NVIC_UNPEND0_INT27 Interrupt 27 unpend 0x8000000 NVIC_UNPEND0_INT28 Interrupt 28 unpend 0x10000000 NVIC_UNPEND0_INT29 Interrupt 29 unpend 0x20000000 NVIC_UNPEND0_INT30 Interrupt 30 unpend 0x40000000 NVIC_UNPEND0_INT31 Interrupt 31 unpend 0x80000000 UNPEND1 Interrupt 32-54 Clear Pending 0x00000284 NVIC_UNPEND1_INT Interrupt Clear Pending [11:0] NVIC_UNPEND1_INT32 Interrupt 32 unpend 0x1 NVIC_UNPEND1_INT33 Interrupt 33 unpend 0x2 NVIC_UNPEND1_INT34 Interrupt 34 unpend 0x4 NVIC_UNPEND1_INT35 Interrupt 35 unpend 0x8 NVIC_UNPEND1_INT36 Interrupt 36 unpend 0x10 NVIC_UNPEND1_INT37 Interrupt 37 unpend 0x20 NVIC_UNPEND1_INT38 Interrupt 38 unpend 0x40 NVIC_UNPEND1_INT39 Interrupt 39 unpend 0x80 NVIC_UNPEND1_INT40 Interrupt 40 unpend 0x100 NVIC_UNPEND1_INT41 Interrupt 41 unpend 0x200 NVIC_UNPEND1_INT42 Interrupt 42 unpend 0x400 NVIC_UNPEND1_INT43 Interrupt 43 unpend 0x800 ACTIVE0 Interrupt 0-31 Active Bit 0x00000300 NVIC_ACTIVE0_INT Interrupt Active [31:0] NVIC_ACTIVE0_INT0 Interrupt 0 active 0x1 NVIC_ACTIVE0_INT1 Interrupt 1 active 0x2 NVIC_ACTIVE0_INT2 Interrupt 2 active 0x4 NVIC_ACTIVE0_INT3 Interrupt 3 active 0x8 NVIC_ACTIVE0_INT4 Interrupt 4 active 0x10 NVIC_ACTIVE0_INT5 Interrupt 5 active 0x20 NVIC_ACTIVE0_INT6 Interrupt 6 active 0x40 NVIC_ACTIVE0_INT7 Interrupt 7 active 0x80 NVIC_ACTIVE0_INT8 Interrupt 8 active 0x100 NVIC_ACTIVE0_INT9 Interrupt 9 active 0x200 NVIC_ACTIVE0_INT10 Interrupt 10 active 0x400 NVIC_ACTIVE0_INT11 Interrupt 11 active 0x800 NVIC_ACTIVE0_INT12 Interrupt 12 active 0x1000 NVIC_ACTIVE0_INT13 Interrupt 13 active 0x2000 NVIC_ACTIVE0_INT14 Interrupt 14 active 0x4000 NVIC_ACTIVE0_INT15 Interrupt 15 active 0x8000 NVIC_ACTIVE0_INT16 Interrupt 16 active 0x10000 NVIC_ACTIVE0_INT17 Interrupt 17 active 0x20000 NVIC_ACTIVE0_INT18 Interrupt 18 active 0x40000 NVIC_ACTIVE0_INT19 Interrupt 19 active 0x80000 NVIC_ACTIVE0_INT20 Interrupt 20 active 0x100000 NVIC_ACTIVE0_INT21 Interrupt 21 active 0x200000 NVIC_ACTIVE0_INT22 Interrupt 22 active 0x400000 NVIC_ACTIVE0_INT23 Interrupt 23 active 0x800000 NVIC_ACTIVE0_INT24 Interrupt 24 active 0x1000000 NVIC_ACTIVE0_INT25 Interrupt 25 active 0x2000000 NVIC_ACTIVE0_INT26 Interrupt 26 active 0x4000000 NVIC_ACTIVE0_INT27 Interrupt 27 active 0x8000000 NVIC_ACTIVE0_INT28 Interrupt 28 active 0x10000000 NVIC_ACTIVE0_INT29 Interrupt 29 active 0x20000000 NVIC_ACTIVE0_INT30 Interrupt 30 active 0x40000000 NVIC_ACTIVE0_INT31 Interrupt 31 active 0x80000000 ACTIVE1 Interrupt 32-54 Active Bit 0x00000304 NVIC_ACTIVE1_INT Interrupt Active [11:0] NVIC_ACTIVE1_INT32 Interrupt 32 active 0x1 NVIC_ACTIVE1_INT33 Interrupt 33 active 0x2 NVIC_ACTIVE1_INT34 Interrupt 34 active 0x4 NVIC_ACTIVE1_INT35 Interrupt 35 active 0x8 NVIC_ACTIVE1_INT36 Interrupt 36 active 0x10 NVIC_ACTIVE1_INT37 Interrupt 37 active 0x20 NVIC_ACTIVE1_INT38 Interrupt 38 active 0x40 NVIC_ACTIVE1_INT39 Interrupt 39 active 0x80 NVIC_ACTIVE1_INT40 Interrupt 40 active 0x100 NVIC_ACTIVE1_INT41 Interrupt 41 active 0x200 NVIC_ACTIVE1_INT42 Interrupt 42 active 0x400 NVIC_ACTIVE1_INT43 Interrupt 43 active 0x800 PRI0 Interrupt 0-3 Priority 0x00000400 NVIC_PRI0_INT0 Interrupt 0 Priority Mask [7:5] NVIC_PRI0_INT1 Interrupt 1 Priority Mask [15:13] NVIC_PRI0_INT2 Interrupt 2 Priority Mask [23:21] NVIC_PRI0_INT3 Interrupt 3 Priority Mask [31:29] PRI1 Interrupt 4-7 Priority 0x00000404 NVIC_PRI1_INT4 Interrupt 4 Priority Mask [7:5] NVIC_PRI1_INT5 Interrupt 5 Priority Mask [15:13] NVIC_PRI1_INT6 Interrupt 6 Priority Mask [23:21] NVIC_PRI1_INT7 Interrupt 7 Priority Mask [31:29] PRI2 Interrupt 8-11 Priority 0x00000408 NVIC_PRI2_INT8 Interrupt 8 Priority Mask [7:5] NVIC_PRI2_INT9 Interrupt 9 Priority Mask [15:13] NVIC_PRI2_INT10 Interrupt 10 Priority Mask [23:21] NVIC_PRI2_INT11 Interrupt 11 Priority Mask [31:29] PRI3 Interrupt 12-15 Priority 0x0000040C NVIC_PRI3_INT12 Interrupt 12 Priority Mask [7:5] NVIC_PRI3_INT13 Interrupt 13 Priority Mask [15:13] NVIC_PRI3_INT14 Interrupt 14 Priority Mask [23:21] NVIC_PRI3_INT15 Interrupt 15 Priority Mask [31:29] PRI4 Interrupt 16-19 Priority 0x00000410 NVIC_PRI4_INT16 Interrupt 16 Priority Mask [7:5] NVIC_PRI4_INT17 Interrupt 17 Priority Mask [15:13] NVIC_PRI4_INT18 Interrupt 18 Priority Mask [23:21] NVIC_PRI4_INT19 Interrupt 19 Priority Mask [31:29] PRI5 Interrupt 20-23 Priority 0x00000414 NVIC_PRI5_INT20 Interrupt 20 Priority Mask [7:5] NVIC_PRI5_INT21 Interrupt 21 Priority Mask [15:13] NVIC_PRI5_INT22 Interrupt 22 Priority Mask [23:21] NVIC_PRI5_INT23 Interrupt 23 Priority Mask [31:29] PRI6 Interrupt 24-27 Priority 0x00000418 NVIC_PRI6_INT24 Interrupt 24 Priority Mask [7:5] NVIC_PRI6_INT25 Interrupt 25 Priority Mask [15:13] NVIC_PRI6_INT26 Interrupt 26 Priority Mask [23:21] NVIC_PRI6_INT27 Interrupt 27 Priority Mask [31:29] PRI7 Interrupt 28-31 Priority 0x0000041C NVIC_PRI7_INT28 Interrupt 28 Priority Mask [7:5] NVIC_PRI7_INT29 Interrupt 29 Priority Mask [15:13] NVIC_PRI7_INT30 Interrupt 30 Priority Mask [23:21] NVIC_PRI7_INT31 Interrupt 31 Priority Mask [31:29] PRI8 Interrupt 32-35 Priority 0x00000420 NVIC_PRI8_INT32 Interrupt 32 Priority Mask [7:5] NVIC_PRI8_INT33 Interrupt 33 Priority Mask [15:13] NVIC_PRI8_INT34 Interrupt 34 Priority Mask [23:21] NVIC_PRI8_INT35 Interrupt 35 Priority Mask [31:29] PRI9 Interrupt 36-39 Priority 0x00000424 NVIC_PRI9_INT36 Interrupt 36 Priority Mask [7:5] NVIC_PRI9_INT37 Interrupt 37 Priority Mask [15:13] NVIC_PRI9_INT38 Interrupt 38 Priority Mask [23:21] NVIC_PRI9_INT39 Interrupt 39 Priority Mask [31:29] PRI10 Interrupt 40-43 Priority 0x00000428 NVIC_PRI10_INT40 Interrupt 40 Priority Mask [7:5] NVIC_PRI10_INT41 Interrupt 41 Priority Mask [15:13] NVIC_PRI10_INT42 Interrupt 42 Priority Mask [23:21] NVIC_PRI10_INT43 Interrupt 43 Priority Mask [31:29] CPUID CPU ID Base 0x00000D00 NVIC_CPUID_REV Revision Number [3:0] NVIC_CPUID_PARTNO Part Number [15:4] NVIC_CPUID_PARTNO_CM3 Cortex-M3 processor 0xc23 NVIC_CPUID_CON Constant [19:16] NVIC_CPUID_VAR Variant Number [23:20] NVIC_CPUID_IMP Implementer Code [31:24] NVIC_CPUID_IMP_ARM ARM 0x41 INT_CTRL Interrupt Control and State 0x00000D04 NVIC_INT_CTRL_VEC_ACT Interrupt Pending Vector Number [5:0] NVIC_INT_CTRL_RET_BASE Return to Base [11:11] NVIC_INT_CTRL_VEC_PEN Interrupt Pending Vector Number [17:12] NVIC_INT_CTRL_VEC_PEN_NMI NMI 0x2 NVIC_INT_CTRL_VEC_PEN_HARD Hard fault 0x3 NVIC_INT_CTRL_VEC_PEN_MEM Memory management fault 0x4 NVIC_INT_CTRL_VEC_PEN_BUS Bus fault 0x5 NVIC_INT_CTRL_VEC_PEN_USG Usage fault 0x6 NVIC_INT_CTRL_VEC_PEN_SVC SVCall 0xb NVIC_INT_CTRL_VEC_PEN_PNDSV PendSV 0xe NVIC_INT_CTRL_VEC_PEN_TICK SysTick 0xf NVIC_INT_CTRL_ISR_PEND Interrupt Pending [22:22] NVIC_INT_CTRL_ISR_PRE Debug Interrupt Handling [23:23] NVIC_INT_CTRL_PENDSTCLR SysTick Clear Pending [25:25] NVIC_INT_CTRL_PENDSTSET SysTick Set Pending [26:26] NVIC_INT_CTRL_UNPEND_SV PendSV Clear Pending [27:27] NVIC_INT_CTRL_PEND_SV PendSV Set Pending [28:28] NVIC_INT_CTRL_NMI_SET NMI Set Pending [31:31] VTABLE Vector Table Offset 0x00000D08 NVIC_VTABLE_OFFSET Vector Table Offset [28:8] NVIC_VTABLE_BASE Vector Table Base [29:29] APINT Application Interrupt and Reset Control 0x00000D0C NVIC_APINT_VECT_RESET System Reset [0:0] NVIC_APINT_VECT_CLR_ACT Clear Active NMI / Fault [1:1] NVIC_APINT_SYSRESETREQ System Reset Request [2:2] NVIC_APINT_PRIGROUP Interrupt Priority Grouping [10:8] NVIC_APINT_PRIGROUP_7_1 Priority group 7.1 split 0x0 NVIC_APINT_PRIGROUP_6_2 Priority group 6.2 split 0x1 NVIC_APINT_PRIGROUP_5_3 Priority group 5.3 split 0x2 NVIC_APINT_PRIGROUP_4_4 Priority group 4.4 split 0x3 NVIC_APINT_PRIGROUP_3_5 Priority group 3.5 split 0x4 NVIC_APINT_PRIGROUP_2_6 Priority group 2.6 split 0x5 NVIC_APINT_PRIGROUP_1_7 Priority group 1.7 split 0x6 NVIC_APINT_PRIGROUP_0_8 Priority group 0.8 split 0x7 NVIC_APINT_ENDIANESS Data Endianess [15:15] NVIC_APINT_VECTKEY Register Key [31:16] NVIC_APINT_VECTKEY Vector key 0x5fa SYS_CTRL System Control 0x00000D10 NVIC_SYS_CTRL_SLEEPEXIT Sleep on ISR Exit [1:1] NVIC_SYS_CTRL_SLEEPDEEP Deep Sleep Enable [2:2] NVIC_SYS_CTRL_SEVONPEND Wake Up on Pending [4:4] CFG_CTRL Configuration and Control 0x00000D14 NVIC_CFG_CTRL_BASE_THR Thread State Control [0:0] NVIC_CFG_CTRL_MAIN_PEND Allow Main Interrupt Trigger [1:1] NVIC_CFG_CTRL_UNALIGNED Trap on Unaligned Access [3:3] NVIC_CFG_CTRL_DIV0 Trap on Divide by 0 [4:4] NVIC_CFG_CTRL_BFHFNMIGN Ignore Bus Fault in NMI and Fault [8:8] NVIC_CFG_CTRL_STKALIGN Stack Alignment on Exception Entry [9:9] SYS_PRI1 System Handler Priority 1 0x00000D18 NVIC_SYS_PRI1_MEM Memory Management Fault Priority [7:5] NVIC_SYS_PRI1_BUS Bus Fault Priority [15:13] NVIC_SYS_PRI1_USAGE Usage Fault Priority [23:21] SYS_PRI2 System Handler Priority 2 0x00000D1C NVIC_SYS_PRI2_SVC SVCall Priority [31:29] SYS_PRI3 System Handler Priority 3 0x00000D20 NVIC_SYS_PRI3_DEBUG Debug Priority [7:5] NVIC_SYS_PRI3_PENDSV PendSV Priority [23:21] NVIC_SYS_PRI3_TICK SysTick Exception Priority [31:29] SYS_HND_CTRL System Handler Control and State 0x00000D24 NVIC_SYS_HND_CTRL_MEMA Memory Management Fault Active [0:0] NVIC_SYS_HND_CTRL_BUSA Bus Fault Active [1:1] NVIC_SYS_HND_CTRL_USGA Usage Fault Active [3:3] NVIC_SYS_HND_CTRL_SVCA SVC Call Active [7:7] NVIC_SYS_HND_CTRL_MON Debug Monitor Active [8:8] NVIC_SYS_HND_CTRL_PNDSV PendSV Exception Active [10:10] NVIC_SYS_HND_CTRL_TICK SysTick Exception Active [11:11] NVIC_SYS_HND_CTRL_USAGEP Usage Fault Pending [12:12] NVIC_SYS_HND_CTRL_MEMP Memory Management Fault Pending [13:13] NVIC_SYS_HND_CTRL_BUSP Bus Fault Pending [14:14] NVIC_SYS_HND_CTRL_SVC SVC Call Pending [15:15] NVIC_SYS_HND_CTRL_MEM Memory Management Fault Enable [16:16] NVIC_SYS_HND_CTRL_BUS Bus Fault Enable [17:17] NVIC_SYS_HND_CTRL_USAGE Usage Fault Enable [18:18] FAULT_STAT Configurable Fault Status 0x00000D28 NVIC_FAULT_STAT_IERR Instruction Access Violation [0:0] NVIC_FAULT_STAT_DERR Data Access Violation [1:1] NVIC_FAULT_STAT_MUSTKE Unstack Access Violation [3:3] NVIC_FAULT_STAT_MSTKE Stack Access Violation [4:4] NVIC_FAULT_STAT_MMARV Memory Management Fault Address Register Valid [7:7] NVIC_FAULT_STAT_IBUS Instruction Bus Error [8:8] NVIC_FAULT_STAT_PRECISE Precise Data Bus Error [9:9] NVIC_FAULT_STAT_IMPRE Imprecise Data Bus Error [10:10] NVIC_FAULT_STAT_BUSTKE Unstack Bus Fault [11:11] NVIC_FAULT_STAT_BSTKE Stack Bus Fault [12:12] NVIC_FAULT_STAT_BFARV Bus Fault Address Register Valid [15:15] NVIC_FAULT_STAT_UNDEF Undefined Instruction Usage Fault [16:16] NVIC_FAULT_STAT_INVSTAT Invalid State Usage Fault [17:17] NVIC_FAULT_STAT_INVPC Invalid PC Load Usage Fault [18:18] NVIC_FAULT_STAT_NOCP No Coprocessor Usage Fault [19:19] NVIC_FAULT_STAT_UNALIGN Unaligned Access Usage Fault [24:24] NVIC_FAULT_STAT_DIV0 Divide-by-Zero Usage Fault [25:25] HFAULT_STAT Hard Fault Status 0x00000D2C NVIC_HFAULT_STAT_VECT Vector Table Read Fault [1:1] NVIC_HFAULT_STAT_FORCED Forced Hard Fault [30:30] NVIC_HFAULT_STAT_DBG Debug Event [31:31] DEBUG_STAT Debug Status Register 0x00000D30 NVIC_DEBUG_STAT_HALTED Halt request [0:0] NVIC_DEBUG_STAT_BKPT Breakpoint instruction [1:1] NVIC_DEBUG_STAT_DWTTRAP DWT match [2:2] NVIC_DEBUG_STAT_VCATCH Vector catch [3:3] NVIC_DEBUG_STAT_EXTRNL EDBGRQ asserted [4:4] MM_ADDR Memory Management Fault Address 0x00000D34 NVIC_MM_ADDR Fault Address [31:0] FAULT_ADDR Bus Fault Address 0x00000D38 NVIC_FAULT_ADDR Fault Address [31:0] MPU_TYPE MPU Type 0x00000D90 NVIC_MPU_TYPE_SEPARATE Separate or Unified MPU [0:0] NVIC_MPU_TYPE_DREGION Number of D Regions [15:8] NVIC_MPU_TYPE_IREGION Number of I Regions [23:16] MPU_CTRL MPU Control 0x00000D94 NVIC_MPU_CTRL_ENABLE MPU Enable [0:0] NVIC_MPU_CTRL_HFNMIENA MPU Enabled During Faults [1:1] NVIC_MPU_CTRL_PRIVDEFEN MPU Default Region [2:2] MPU_NUMBER MPU Region Number 0x00000D98 NVIC_MPU_NUMBER MPU Region to Access [2:0] MPU_BASE MPU Region Base Address 0x00000D9C NVIC_MPU_BASE_REGION Region Number [2:0] NVIC_MPU_BASE_VALID Region Number Valid [4:4] NVIC_MPU_BASE_ADDR Base Address Mask [31:5] MPU_ATTR MPU Region Attribute and Size 0x00000DA0 NVIC_MPU_ATTR_ENABLE Region Enable [0:0] NVIC_MPU_ATTR_SIZE Region Size Mask [5:1] NVIC_MPU_ATTR_SIZE_32B Region size 32 bytes 0x4 NVIC_MPU_ATTR_SIZE_64B Region size 64 bytes 0x5 NVIC_MPU_ATTR_SIZE_128B Region size 128 bytes 0x6 NVIC_MPU_ATTR_SIZE_256B Region size 256 bytes 0x7 NVIC_MPU_ATTR_SIZE_512B Region size 512 bytes 0x8 NVIC_MPU_ATTR_SIZE_1K Region size 1 Kbytes 0x9 NVIC_MPU_ATTR_SIZE_2K Region size 2 Kbytes 0xa NVIC_MPU_ATTR_SIZE_4K Region size 4 Kbytes 0xb NVIC_MPU_ATTR_SIZE_8K Region size 8 Kbytes 0xc NVIC_MPU_ATTR_SIZE_16K Region size 16 Kbytes 0xd NVIC_MPU_ATTR_SIZE_32K Region size 32 Kbytes 0xe NVIC_MPU_ATTR_SIZE_64K Region size 64 Kbytes 0xf NVIC_MPU_ATTR_SIZE_128K Region size 128 Kbytes 0x10 NVIC_MPU_ATTR_SIZE_256K Region size 256 Kbytes 0x11 NVIC_MPU_ATTR_SIZE_512K Region size 512 Kbytes 0x12 NVIC_MPU_ATTR_SIZE_1M Region size 1 Mbytes 0x13 NVIC_MPU_ATTR_SIZE_2M Region size 2 Mbytes 0x14 NVIC_MPU_ATTR_SIZE_4M Region size 4 Mbytes 0x15 NVIC_MPU_ATTR_SIZE_8M Region size 8 Mbytes 0x16 NVIC_MPU_ATTR_SIZE_16M Region size 16 Mbytes 0x17 NVIC_MPU_ATTR_SIZE_32M Region size 32 Mbytes 0x18 NVIC_MPU_ATTR_SIZE_64M Region size 64 Mbytes 0x19 NVIC_MPU_ATTR_SIZE_128M Region size 128 Mbytes 0x1a NVIC_MPU_ATTR_SIZE_256M Region size 256 Mbytes 0x1b NVIC_MPU_ATTR_SIZE_512M Region size 512 Mbytes 0x1c NVIC_MPU_ATTR_SIZE_1G Region size 1 Gbytes 0x1d NVIC_MPU_ATTR_SIZE_2G Region size 2 Gbytes 0x1e NVIC_MPU_ATTR_SIZE_4G Region size 4 Gbytes 0x1f NVIC_MPU_ATTR_SRD Subregion Disable Bits [15:8] NVIC_MPU_ATTR_SRD_0 Sub-region 0 disable 0x1 NVIC_MPU_ATTR_SRD_1 Sub-region 1 disable 0x2 NVIC_MPU_ATTR_SRD_2 Sub-region 2 disable 0x4 NVIC_MPU_ATTR_SRD_3 Sub-region 3 disable 0x8 NVIC_MPU_ATTR_SRD_4 Sub-region 4 disable 0x10 NVIC_MPU_ATTR_SRD_5 Sub-region 5 disable 0x20 NVIC_MPU_ATTR_SRD_6 Sub-region 6 disable 0x40 NVIC_MPU_ATTR_SRD_7 Sub-region 7 disable 0x80 NVIC_MPU_ATTR_BUFFRABLE Bufferable [16:16] NVIC_MPU_ATTR_CACHEABLE Cacheable [17:17] NVIC_MPU_ATTR_SHAREABLE Shareable [18:18] NVIC_MPU_ATTR_TEX Type Extension Mask [21:19] NVIC_MPU_ATTR_AP Access Privilege [26:24] NVIC_MPU_ATTR_AP_NO_NO prv: no access, usr: no access 0x0 NVIC_MPU_ATTR_AP_RW_NO prv: rw, usr: none 0x1 NVIC_MPU_ATTR_AP_RW_RO prv: rw, usr: read-only 0x2 NVIC_MPU_ATTR_AP_RW_RW prv: rw, usr: rw 0x3 NVIC_MPU_ATTR_AP_RO_NO prv: ro, usr: none 0x5 NVIC_MPU_ATTR_AP_RO_RO prv: ro, usr: ro 0x6 NVIC_MPU_ATTR_XN Instruction Access Disable [28:28] MPU_BASE1 MPU Region Base Address Alias 1 0x00000DA4 NVIC_MPU_BASE1_REGION Region Number [2:0] NVIC_MPU_BASE1_VALID Region Number Valid [4:4] NVIC_MPU_BASE1_ADDR Base Address Mask [31:5] MPU_ATTR1 MPU Region Attribute and Size Alias 1 0x00000DA8 NVIC_MPU_ATTR1_ENABLE Region Enable [0:0] NVIC_MPU_ATTR1_SIZE Region Size Mask [5:1] NVIC_MPU_ATTR1_SRD Subregion Disable Bits [15:8] NVIC_MPU_ATTR1_BUFFRABLE Bufferable [16:16] NVIC_MPU_ATTR1_CACHEABLE Cacheable [17:17] NVIC_MPU_ATTR1_SHAREABLE Shareable [18:18] NVIC_MPU_ATTR1_TEX Type Extension Mask [21:19] NVIC_MPU_ATTR1_AP Access Privilege [26:24] NVIC_MPU_ATTR1_XN Instruction Access Disable [28:28] MPU_BASE2 MPU Region Base Address Alias 2 0x00000DAC NVIC_MPU_BASE2_REGION Region Number [2:0] NVIC_MPU_BASE2_VALID Region Number Valid [4:4] NVIC_MPU_BASE2_ADDR Base Address Mask [31:5] MPU_ATTR2 MPU Region Attribute and Size Alias 2 0x00000DB0 NVIC_MPU_ATTR2_ENABLE Region Enable [0:0] NVIC_MPU_ATTR2_SIZE Region Size Mask [5:1] NVIC_MPU_ATTR2_SRD Subregion Disable Bits [15:8] NVIC_MPU_ATTR2_BUFFRABLE Bufferable [16:16] NVIC_MPU_ATTR2_CACHEABLE Cacheable [17:17] NVIC_MPU_ATTR2_SHAREABLE Shareable [18:18] NVIC_MPU_ATTR2_TEX Type Extension Mask [21:19] NVIC_MPU_ATTR2_AP Access Privilege [26:24] NVIC_MPU_ATTR2_XN Instruction Access Disable [28:28] MPU_BASE3 MPU Region Base Address Alias 3 0x00000DB4 NVIC_MPU_BASE3_REGION Region Number [2:0] NVIC_MPU_BASE3_VALID Region Number Valid [4:4] NVIC_MPU_BASE3_ADDR Base Address Mask [31:5] MPU_ATTR3 MPU Region Attribute and Size Alias 3 0x00000DB8 NVIC_MPU_ATTR3_ENABLE Region Enable [0:0] NVIC_MPU_ATTR3_SIZE Region Size Mask [5:1] NVIC_MPU_ATTR3_SRD Subregion Disable Bits [15:8] NVIC_MPU_ATTR3_BUFFRABLE Bufferable [16:16] NVIC_MPU_ATTR3_CACHEABLE Cacheable [17:17] NVIC_MPU_ATTR3_SHAREABLE Shareable [18:18] NVIC_MPU_ATTR3_TEX Type Extension Mask [21:19] NVIC_MPU_ATTR3_AP Access Privilege [26:24] NVIC_MPU_ATTR3_XN Instruction Access Disable [28:28] DBG_CTRL Debug Control and Status Reg 0x00000DF0 NVIC_DBG_CTRL_C_DEBUGEN Enable debug [0:0] NVIC_DBG_CTRL_C_HALT Halt the core [1:1] NVIC_DBG_CTRL_C_STEP Step the core [2:2] NVIC_DBG_CTRL_C_MASKINT Mask interrupts when stepping [3:3] NVIC_DBG_CTRL_C_SNAPSTALL Breaks a stalled load/store [5:5] NVIC_DBG_CTRL_S_REGRDY Register read/write available [16:16] NVIC_DBG_CTRL_S_HALT Core status on halt [17:17] NVIC_DBG_CTRL_S_SLEEP Core is sleeping [18:18] NVIC_DBG_CTRL_S_LOCKUP Core is locked up [19:19] NVIC_DBG_CTRL_S_RETIRE_ST Core has executed insruction since last read [24:24] NVIC_DBG_CTRL_S_RESET_ST Core has reset since last read [25:25] DBG_XFER Debug Core Reg. Transfer Select 0x00000DF4 NVIC_DBG_XFER_REG_SEL Register [4:0] NVIC_DBG_XFER_REG_R0 Register R0 0x0 NVIC_DBG_XFER_REG_R1 Register R1 0x1 NVIC_DBG_XFER_REG_R2 Register R2 0x2 NVIC_DBG_XFER_REG_R3 Register R3 0x3 NVIC_DBG_XFER_REG_R4 Register R4 0x4 NVIC_DBG_XFER_REG_R5 Register R5 0x5 NVIC_DBG_XFER_REG_R6 Register R6 0x6 NVIC_DBG_XFER_REG_R7 Register R7 0x7 NVIC_DBG_XFER_REG_R8 Register R8 0x8 NVIC_DBG_XFER_REG_R9 Register R9 0x9 NVIC_DBG_XFER_REG_R10 Register R10 0xa NVIC_DBG_XFER_REG_R11 Register R11 0xb NVIC_DBG_XFER_REG_R12 Register R12 0xc NVIC_DBG_XFER_REG_R13 Register R13 0xd NVIC_DBG_XFER_REG_R14 Register R14 0xe NVIC_DBG_XFER_REG_R15 Register R15 0xf NVIC_DBG_XFER_REG_FLAGS xPSR/Flags register 0x10 NVIC_DBG_XFER_REG_MSP Main SP 0x11 NVIC_DBG_XFER_REG_PSP Process SP 0x12 NVIC_DBG_XFER_REG_DSP Deep SP 0x13 NVIC_DBG_XFER_REG_CFBP Control/Fault/BasePri/PriMask 0x14 NVIC_DBG_XFER_REG_WNR Write or not read [16:16] DBG_DATA Debug Core Register Data 0x00000DF8 NVIC_DBG_DATA Data temporary cache [31:0] DBG_INT Debug Reset Interrupt Control 0x00000DFC NVIC_DBG_INT_RSTVCATCH Reset vector catch [0:0] NVIC_DBG_INT_RSTPENDING Core reset is pending [1:1] NVIC_DBG_INT_RSTPENDCLR Clear pending core reset [2:2] NVIC_DBG_INT_RESET Core reset status [3:3] NVIC_DBG_INT_MMERR Debug trap on mem manage fault [4:4] NVIC_DBG_INT_NOCPERR Debug trap on coprocessor error [5:5] NVIC_DBG_INT_CHKERR Debug trap on usage fault check [6:6] NVIC_DBG_INT_STATERR Debug trap on usage fault state [7:7] NVIC_DBG_INT_BUSERR Debug trap on bus error [8:8] NVIC_DBG_INT_INTERR Debug trap on interrupt errors [9:9] NVIC_DBG_INT_HARDERR Debug trap on hard fault [10:10] SW_TRIG Software Trigger Interrupt 0x00000F00 write-only NVIC_SW_TRIG_INTID Interrupt ID [5:0] write-only FLASH FLASH Memory Map for lm3s6965 0x00000000 0 0x00040000 FLASH Memory SRAM SRAM Memory Map for lm3s6965 0x20000000 0 0x00010000 SRAM